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? 2007 microchip technology inc. preliminary ds70152d-page 1 DSPIC33F/pic24h 1.0 device overview this document defines the programming specification for the DSPIC33F 16-bit digital signal controller (dsc) and pic24h 16-bit microcontroller (mcu) families. this programming specification is required only for those developing programming support for the DSPIC33F/ pic24h family. customers only using one of these devices should use development tools that already provide support for device programming. this document includes programming specifications for the following devices: ? DSPIC33Fj64gp206 ? DSPIC33Fj64gp306 ? DSPIC33Fj64gp310 ? DSPIC33Fj64gp706 ? DSPIC33Fj64gp708 ? DSPIC33Fj64gp710 ? DSPIC33Fj128gp206 ? DSPIC33Fj128gp306 ? DSPIC33Fj128gp310 ? DSPIC33Fj128gp706 ? DSPIC33Fj128gp708 ? DSPIC33Fj128gp710 ? DSPIC33Fj256gp506 ? DSPIC33Fj256gp510 ? DSPIC33Fj256gp710 ? DSPIC33Fj64mc506 ? DSPIC33Fj64mc508 ? DSPIC33Fj64mc510 ? DSPIC33Fj64mc706 ? DSPIC33Fj64mc710 ? DSPIC33Fj128mc506 ? DSPIC33Fj128mc510 ? DSPIC33Fj128mc706 ? DSPIC33Fj128mc708 ? DSPIC33Fj128mc710 ? DSPIC33Fj256mc510 ? DSPIC33Fj256mc710 ? pic24hj64gp206 ? pic24hj64gp210 ? pic24hj64gp506 ? pic24hj64gp510 ? pic24hj128gp206 ? pic24hj128gp210 ? pic24hj128gp306 ? pic24hj128gp310 ? pic24hj128gp506 ? pic24hj128gp510 ? pic24hj256gp206 ? pic24hj256gp210 ? pic24hj256gp610 ? DSPIC33Fj12gp201 ? DSPIC33Fj12gp202 ? DSPIC33Fj12mc201 ? DSPIC33Fj12mc202 ? pic24hj12gp201 ? pic24hj12gp202 2.0 programming overview of the DSPIC33F/pic24h there are two methods of programming the DSPIC33F/ pic24h family of devices discussed in this programming specification. they are: ? in-circuit serial programming? (icsp?) programming capability ? enhanced in-circuit serial programming the icsp programming method is the most direct method to program the device; however, it is also the slower of the two methods. it provides native, low-level programming capability to erase, program and verify the chip. the enhanced icsp protocol uses a faster method that takes advantage of the programming executive, as illustrated in figure 2-1. the programming executive provides all the necessary functionality to erase, pro- gram and verify the chip through a small command set. the command set allows the programmer to program the DSPIC33F/pic24h programming specification devices without having to deal with the low-level programming protocols of the chip. DSPIC33F/pic24h flash pr ogramming specification
DSPIC33F/pic24h programming specification ds70152d-page 2 preliminary ? 2007 microchip technology inc. figure 2-1: programming system overview for enhanced icsp? this specification is divided into major sections that describe the programming methods independently. section 3.0 ?device programming ? enhanced icsp? describes the enhanced icsp method. section 5.0 ?device programming ? icsp? describes the icsp method. 2.1 power requirements all devices in the DSPIC33F/pic24h family are dual volt- age supply designs: one supply for the core and another for the peripherals and i/o pins. a regulator is provided on-chip to alleviate the need for two external voltage supplies. all of the DSPIC33F/pic24h devices power their core digital logic at a nominal 2.5v. to simplify system design, all devices in the DSPIC33F/pic24h program- ming specification family incorporate an on-chip regu- lator that allows the device to run its core logic from v dd . the regulator provides power to the core from the other v dd pins. a low-esr capacitor (such as tantalum) must be connected to the v ddcore pin (figure 2-2). this helps to maintain the stability of the regulator. the specifications for core voltage and capacitance are listed in section table 8-1: ?ac/dc characteristics and timing requirements? . figure 2-2: connections for the on-chip regulator 2.2 program memory write/erase requirements the program flash memory on the DSPIC33F/pic24h has a specific write/erase requirement that must be adhered to for proper device operation. the rule is that any given word in memory must not be written without first erasing the page in which it is located. thus, the easiest way to conform to this rule is to write all the data in a programming block within one write cycle. the pro- gramming methods specified in this document comply with this requirement. DSPIC33F/pic24h programmer programming executive on-chip memory note: a program memory word can be pro- grammed twice before an erase, but only if (a) the same data is used in both pro- gram operations or (b) bits containing ? 1 ? are set to ? 0 ? but no ? 0 ? is set to ? 1 ?. note 1: these are typical operating voltages. refer to section table 8-1: ?ac/dc charac- teristics and timing requirements? for the full operating ranges of v dd and v dd v ddcore v ss DSPIC33F/pic24h c f 3.3v
? 2007 microchip technology inc. preliminary ds70152d-page 3 DSPIC33F/pic24h prog ramming specification 2.3 pin diagrams the pin diagrams for the DSPIC33F/pic24h device family are shown in the following figures. the pins that are required for programming are listed in table 2-1. the mclr , pgc1, pgd1, pgc2, pgd2, pgc3 and pgd3 pins are shown in bold letters in the figures. refer to the appropriate device data sheet for complete pin descriptions. table 2-1: pin descriptions (pins used during programming) pin name during programming pin name pin type pin description mclr mclr p programming enable v dd and av dd (1) v dd p power supply v ss and av ss (1) v ss pground v ddcore v ddcore p regulated power supply for core pgc1 pgc1 i primary programming pin pair: serial clock pgd1 pgd1 i/o primary programming pin pair: serial data pgc2 pgc2 i secondary programming pin pair: serial clock pgd2 pgd2 i/o secondary programming pin pair: serial data pgc3 pgc3 i tertiary programming pin pair: serial clock pgd3 pgd3 i/o tertiary programming pin pair: serial data legend: i = input, o = output, p = power note 1: all power supply and ground pins must be connected, including analog supplies (av dd ) and ground (av ss ).
DSPIC33F/pic24h programming specification ds70152d-page 4 preliminary ? 2007 microchip technology inc. pin diagrams 64-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 36 35 34 33 32 31 30 29 28 27 26 64 63 62 61 60 59 58 57 56 14 15 16 17 18 19 20 21 22 23 24 25 pgc2 /emuc2/sosco/t1ck/cn0/rc1 4 pgd2 /emud2/sosci/t4ck/cn1/rc13 oc1/rd0 ic4/int4/rd11 ic2/u1cts /int2/rd9 ic1/int1/rd8 v ss osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 u1rts /sck1/int0/rf6 u1rx/sdi1/rf2 u1tx/sdo1/rf3 cofs/rg15 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr v ss v dd an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 pgc3 /emuc3/an1/v ref -/cn3/rb1 pgd3 /emud3/an0/v ref +/cn2/rb0 oc8/cn16/rd7 csdo/rg13 csdi/rg12 csck/rg14 v ddcore rg1 rf1 rg0 oc2/rd1 oc3/rd2 pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 av dd av ss u2cts /an8/rb8 an9/rb9 tms/an10/rb10 tdo/an11/rb11 v ss v dd tck/an12/rb12 tdi/an13/rb13 u2rts /an14/rb14 an15/ocfb/cn12/rb15 u2tx/cn18/rf5 u2rx / cn17/rf4 sda1/rg3 43 42 41 40 39 38 37 44 48 47 46 50 49 51 54 53 52 55 45 ss2 /t5ck/cn11/rg9 an5/ic8/cn7/rb5 an4/ic7/cn6/rb4 ic3/int3/rd10 v dd rf0 oc4/rd3 oc7/cn15/rd6 oc6/ic6/cn14/rd5 oc5/ic5/cn13/rd4 DSPIC33Fj64gp206 DSPIC33Fj128gp206
? 2007 microchip technology inc. preliminary ds70152d-page 5 DSPIC33F/pic24h prog ramming specification pin diagrams (continued) 64-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 36 35 34 33 32 31 30 29 28 27 26 64 63 62 61 60 59 58 57 56 14 15 16 17 18 19 20 21 22 23 24 25 pgc2 /emuc2/sosco/t1ck/cn0/rc1 4 pgd2 /emud2/sosci/t4ck/cn1/rc13 oc1/rd0 ic4/int4/rd11 ic2/u1cts /int2/rd9 ic1/int1/rd8 v ss osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 u1rts /sck1/int0/rf6 u1rx/sdi1/rf2 u1tx/sdo1/rf3 cofs/rg15 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr v ss v dd an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 pgc3 /emuc3/an1/v ref -/cn3/rb1 pgd3 /emud3/an0/v ref +/cn2/rb0 oc8/cn16/rd7 csdo/rg13 csdi/rg12 csck/rg14 v ddcore rg1 rf1 rg0 oc2/rd1 oc3/rd2 pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 av dd av ss u2cts /an8/rb8 an9/rb9 tms/an10/rb10 tdo/an11/rb11 v ss v dd tck/an12/rb12 tdi/an13/rb13 u2rts /an14/rb14 an15/ocfb/cn12/rb15 u2tx/scl2/cn18/rf5 u2rx / sda2/cn17/rf4 sda1/rg3 43 42 41 40 39 38 37 44 48 47 46 50 49 51 54 53 52 55 45 ss2 /t5ck/cn11/rg9 an5/ic8/cn7/rb5 an4/ic7/cn6/rb4 ic3/int3/rd10 v dd rf0 oc4/rd3 oc7/cn15/rd6 oc6/ic6/cn14/rd5 oc5/ic5/cn13/rd4 DSPIC33Fj64gp306 DSPIC33Fj128gp306
DSPIC33F/pic24h programming specification ds70152d-page 6 preliminary ? 2007 microchip technology inc. pin diagrams (continued) 64-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 36 35 34 33 32 31 30 29 28 27 26 64 63 62 61 60 59 58 57 56 14 15 16 17 18 19 20 21 22 23 24 25 pgc2 /emuc2/sosco/t1ck/cn0/rc1 4 pgd2 /emud2/sosci/t4ck/cn1/rc13 oc1/rd0 ic4/int4/rd11 ic2/u1cts /int2/rd9 ic1/int1/rd8 v ss osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 u1rts /sck1/int0/rf6 u1rx/sdi1/rf2 u1tx/sdo1/rf3 cofs/rg15 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr v ss v dd an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 pgc3 /emuc3/an1/v ref -/cn3/rb1 pgd3 /emud3/an0/v ref +/cn2/rb0 oc8/cn16/rd7 csdo/rg13 csdi/rg12 csck/rg14 v ddcore rg1 c1tx/rf1 rg0 oc2/rd1 oc3/rd2 pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 av dd av ss u2cts /an8/rb8 an9/rb9 tms/an10/rb10 tdo/an11/rb11 v ss v dd tck/an12/rb12 tdi/an13/rb13 u2rts /an14/rb14 an15/ocfb/cn12/rb15 u2tx/scl2/cn18/rf5 u2rx / sda2/cn17/rf4 sda1/rg3 43 42 41 40 39 38 37 44 48 47 46 50 49 51 54 53 52 55 45 ss2 /t5ck/cn11/rg9 an5/ic8/cn7/rb5 an4/ic7/cn6/rb4 ic3/int3/rd10 v dd c1rx/rf0 oc4/rd3 oc7/cn15/rd6 oc6/ic6/cn14/rd5 oc5/ic5/cn13/rd4 DSPIC33Fj256gp506
? 2007 microchip technology inc. preliminary ds70152d-page 7 DSPIC33F/pic24h prog ramming specification pin diagrams (continued) 64-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 36 35 34 33 32 31 30 29 28 27 26 64 63 62 61 60 59 58 57 56 14 15 16 17 18 19 20 21 22 23 24 25 pgc2 /emuc2/sosco/t1ck/cn0/rc1 4 pgd2 /emud2/sosci/t4ck/cn1/rc13 oc1/rd0 ic4/int4/rd11 ic2/u1cts /int2/rd9 ic1/int1/rd8 v ss osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 u1rts /sck1/int0/rf6 u1rx/sdi1/rf2 u1tx/sdo1/rf3 cofs/rg15 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr v ss v dd an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 pgc3 /emuc3/an1/v ref -/cn3/rb1 pgd3 /emud3/an0/v ref +/cn2/rb0 oc8/cn16/rd7 csdo/rg13 csdi/rg12 csck/rg14 v ddcore c2tx/rg1 c1tx/rf1 c2rx/rg0 oc2/rd1 oc3/rd2 pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 av dd av ss u2cts /an8/rb8 an9/rb9 tms/an10/rb10 tdo/an11/rb11 v ss v dd tck/an12/rb12 tdi/an13/rb13 u2rts /an14/rb14 an15/ocfb/cn12/rb15 u2tx/scl2/cn18/rf5 u2rx / sda2/cn17/rf4 sda1/rg3 43 42 41 40 39 38 37 44 48 47 46 50 49 51 54 53 52 55 45 ss2 /t5ck/cn11/rg9 an5/ic8/cn7/rb5 an4/ic7/cn6/rb4 ic3/int3/rd10 v dd c1rx/rf0 oc4/rd3 oc7/cn15/rd6 oc6/ic6/cn14/rd5 oc5/ic5/cn13/rd4 DSPIC33Fj64gp706 DSPIC33Fj128gp706
DSPIC33F/pic24h programming specification ds70152d-page 8 preliminary ? 2007 microchip technology inc. pin diagrams (continued) 80-pin tqfp 72 74 73 71 70 69 68 67 66 65 64 63 62 61 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 50 49 48 47 46 45 44 21 41 40 39 38 37 36 35 34 23 24 25 26 27 28 29 30 31 32 33 DSPIC33Fj64gp708 17 18 19 75 1 57 56 55 54 53 52 51 60 59 58 43 42 76 78 77 79 22 80 ic5/rd12 oc4/rd3 oc3/rd2 oc2/rd1 csck/rg14 an23/cn23/ra7 an22/cn22/ra6 c2rx/rg0 c2tx/rg1 c1tx/rf1 c1rx/rf0 csdo/rg13 csdi/rg12 oc8/cn16/rd7 oc6/cn14/rd5 oc1/rd0 ic4/rd11 ic2/rd9 ic1/rd8 ic3/rd10 v ss osc1/clkin/rc12 v dd scl1/rg2 u1rx/rf2 u1tx/rf3 pgc2 /emuc2/sosco/t1ck/ pgd2 /emud2/sosci/cn1/rc1 3 v ref +/ra10 v ref -/ra9 av dd av ss u2cts /an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2rx/cn17/rf4 ic8/u1rts /cn21/rd15 u2tx/cn18/rf5 pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 an17/t3ck/t6ck/rc2 an18/t4ck/t9ck/rc3 an19/t5ck/t8ck/rc4 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr ss2 /cn11/rg9 an4/cn6/rb4 an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 pgc3 /emuc3/an1/cn3/rb1 pgd3 /emud3/an0/cn2/rb0 v ss v dd cofs/rg15 an16/t2ck/t7ck/rc1 tdo/an21/int2/ra13 tms/an20/int1/ra12 tck/an12/rb12 tdi/an13/rb13 u2rts /an14/rb14 an15/ocfb/cn12/rb15 v dd v ddcore oc5/cn13/rd4 ic6/cn19/rd13 sda1/rg3 sdi1/rf7 sdo1/rf8 an5/cn7/rb5 v ss osc2/clko/rc15 oc7/cn15/rd6 sck1/int0/rf6 ic7/u1cts /cn20/rd14 sda2/int4/ra3 scl2/int3/ra2 DSPIC33Fj128gp708 cn0/rc14
? 2007 microchip technology inc. preliminary ds70152d-page 9 DSPIC33F/pic24h prog ramming specification pin diagrams (continued) 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 26 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 95 1 76 77 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 96 98 97 99 27 46 47 48 49 50 55 54 53 52 51 oc6/cn14/rd5 oc5/cn13/rd4 ic6/cn19/rd13 ic5/rd12 oc4/rd3 oc3/rd2 oc2/rd1 an23/cn23/ra7 an22/cn22/ra6 an26/re2 csdo/rg13 csdi/rg12 csck/rg14 an25/re1 an24/re0 rg0 an28/re4 an27/re3 rf0 v ddcore pgd2 / emud2/sosci/cn1/rc13 oc1/rd0 ic3/rd10 ic2/rd9 ic1/rd8 ic4/rd11 sda2/ra3 scl2/ra2 osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 sck1/int0/rf6 sdi1/rf7 sdo1/rf8 sda1/rg3 u1rx/rf2 u1tx/rf3 v ss pgc2 / emuc2/sosco/t1ck/cn0/rc1 4 v ref +/ra10 v ref -/ra9 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2cts /rf12 u2rts /rf13 ic7/ u1cts /cn20/rd14 ic8/ u1rts /cn21/rd15 v dd v ss pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 u2tx/cn18/rf5 u2rx/cn17/rf4 an29/re5 an30/re6 an31/re7 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 an18/t4ck/t9ck/rc3 an19/t5ck/t8ck/rc4 sck2/cn8/rg6 v dd tms/ra0 an20/int1/ra12 an21/int2/ra13 an5/cn7/rb5 an4/cn6/rb4 an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 sdi2/cn9/rg7 sdo2/cn10/rg8 pgc3 /emuc3/ an1/cn3/rb1 pgd3 /emud3/ an0/cn2/rb0 cofs/rg15 v dd ss2 /cn11/rg9 mclr an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 rg1 rf1 oc8/cn16/rd7 oc7/cn15/rd6 tdo/ra5 int4/ra15 int3/ra14 v ss v ss v ss v dd tdi/ra4 tck/ra1 100-pin tqfp DSPIC33Fj64gp310 DSPIC33Fj128gp310 100
DSPIC33F/pic24h programming specification ds70152d-page 10 preliminary ? 2007 microchip technology inc. pin diagrams (continued) 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 26 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 95 1 76 77 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 96 98 97 99 27 46 47 48 49 50 55 54 53 52 51 oc6/cn14/rd5 oc5/cn13/rd4 ic6/cn19/rd13 ic5/rd12 oc4/rd3 oc3/rd2 oc2/rd1 an23/cn23/ra7 an22/cn22/ra6 an26/re2 csdo/rg13 csdi/rg12 csck/rg14 an25/re1 an24/re0 rg0 an28/re4 an27/re3 c1rx/rf0 v ddcore pgd2 / emud2/sosci/cn1/rc13 oc1/rd0 ic3/rd10 ic2/rd9 ic1/rd8 ic4/rd11 sda2/ra3 scl2/ra2 osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 sck1/int0/rf6 sdi1/rf7 sdo1/rf8 sda1/rg3 u1rx/rf2 u1tx/rf3 v ss pgc2 / emuc2/sosco/t1ck/cn0/rc1 4 v ref +/ra10 v ref -/ra9 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2cts /rf12 u2rts /rf13 ic7/ u1cts /cn20/rd14 ic8/ u1rts /cn21/rd15 v dd v ss pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 u2tx/cn18/rf5 u2rx/cn17/rf4 an29/re5 an30/re6 an31/re7 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 an18/t4ck/t9ck/rc3 an19/t5ck/t8ck/rc4 sck2/cn8/rg6 v dd tms/ra0 an20/int1/ra12 an21/int2/ra13 an5/cn7/rb5 an4/cn6/rb4 an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 sdi2/cn9/rg7 sdo2/cn10/rg8 pgc3 /emuc3/ an1/cn3/rb1 pgd3 /emud3/ an0/cn2/rb0 cofs/rg15 v dd ss2 /cn11/rg9 mclr an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 rg1 c1tx/rf1 oc8/cn16/rd7 oc7/cn15/rd6 tdo/ra5 int4/ra15 int3/ra14 v ss v ss v ss v dd tdi/ra4 tck/ra1 100-pin tqfp DSPIC33Fj256gp510 100
? 2007 microchip technology inc. preliminary ds70152d-page 11 DSPIC33F/pic24h prog ramming specification pin diagrams (continued) 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 26 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 95 1 76 77 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 96 98 97 99 27 46 47 48 49 50 55 54 53 52 51 oc6/cn14/rd5 oc5/cn13/rd4 ic6/cn19/rd13 ic5/rd12 oc4/rd3 oc3/rd2 oc2/rd1 an23/cn23/ra7 an22/cn22/ra6 an26/re2 csdo/rg13 csdi/rg12 csck/rg14 an25/re1 an24/re0 c2rx/rg0 an28/re4 an27/re3 c1rx/rf0 v ddcore pgd2 / emud2/sosci/cn1/rc13 oc1/rd0 ic3/rd10 ic2/rd9 ic1/rd8 ic4/rd11 sda2/ra3 scl2/ra2 osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 sck1/int0/rf6 sdi1/rf7 sdo1/rf8 sda1/rg3 u1rx/rf2 u1tx/rf3 v ss pgc2 / emuc2/sosco/t1ck/cn0/rc1 4 v ref +/ra10 v ref -/ra9 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2cts /rf12 u2rts /rf13 ic7/ u1cts /cn20/rd14 ic8/ u1rts /cn21/rd15 v dd v ss pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 u2tx/cn18/rf5 u2rx/cn17/rf4 an29/re5 an30/re6 an31/re7 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 an18/t4ck/t9ck/rc3 an19/t5ck/t8ck/rc4 sck2/cn8/rg6 v dd tms/ra0 an20/int1/ra12 an21/int2/ra13 an5/cn7/rb5 an4/cn6/rb4 an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 sdi2/cn9/rg7 sdo2/cn10/rg8 pgc3 /emuc3/ an1/cn3/rb1 pgd3 /emud3/ an0/cn2/rb0 cofs/rg15 v dd ss2 /cn11/rg9 mclr an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 c2tx/rg1 c1tx/rf1 oc8/cn16/rd7 oc7/cn15/rd6 tdo/ra5 int4/ra15 int3/ra14 v ss v ss v ss v dd tdi/ra4 tck/ra1 100-pin tqfp DSPIC33Fj128gp710 100 DSPIC33Fj256gp710 DSPIC33Fj64gp710
DSPIC33F/pic24h programming specification ds70152d-page 12 preliminary ? 2007 microchip technology inc. pin diagrams (continued) 64-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 36 35 34 33 32 31 30 29 28 27 26 64 63 62 61 60 59 58 57 56 14 15 16 17 18 19 20 21 22 23 24 25 pgc2 /emuc2/sosco/t1ck/cn0/rc14 pgd2 /emud2/sosci/t4ck/cn1/rc13 oc1/rd0 ic4/int4/rd11 ic2/u1cts /fltb/int2/rd9 ic1/flta/int1/rd8 v ss osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 u1rts /sck1/int0/rf6 u1rx/sdi1/rf2 u1tx/sdo1/rf3 pwm3h/re5 pwm4l/re6 pwm4h/re7 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr v ss v dd an3/indx/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 pgc3 /emuc3/an1/v ref -/cn3/rb1 pgd3 /emud3/an0/v ref +/cn2/rb0 oc8/updn/cn16/rd7 pwm3l/re4 pwm2h/re3 pwm2l/re2 v ddcore pwm1l/re0 c1tx/rf1 pwm1h/re1 oc2/rd1 oc3/rd2 pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 av dd av ss u2cts /an8/rb8 an9/rb9 tms/an10/rb10 tdo/an11/rb11 v ss v dd tck/an12/rb12 tdi/an13/rb13 u2rts /an14/rb14 an15/ocfb/cn12/rb15 u2tx/cn18/rf5 u2rx / cn17/rf4 sda1/rg3 43 42 41 40 39 38 37 44 48 47 46 50 49 51 54 53 52 55 45 ss2 /t5ck/cn11/rg9 an5/qeb/ic8/cn7/rb5 an4/qea/ic7/cn6/rb4 ic3/int3/rd10 v dd c1rx/rf0 oc4/rd3 oc7/cn15/rd6 oc6/ic6/cn14/rd5 oc5/ic5/cn13/rd4 DSPIC33Fj64mc506
? 2007 microchip technology inc. preliminary ds70152d-page 13 DSPIC33F/pic24h prog ramming specification pin diagrams (continued) 64-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 36 35 34 33 32 31 30 29 28 27 26 64 63 62 61 60 59 58 57 56 14 15 16 17 18 19 20 21 22 23 24 25 pgc2 /emuc2/sosco/t1ck/cn0/rc14 pgd2 /emud2/sosci/t4ck/cn1/rc13 oc1/rd0 ic4/int4/rd11 ic2/u1cts /fltb/int2/rd9 ic1/flta/int1/rd8 v ss osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 u1rts /sck1/int0/rf6 u1rx/sdi1/rf2 u1tx/sdo1/rf3 pwm3h/re5 pwm4l/re6 pwm4h/re7 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr v ss v dd an3/indx/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 pgc3 /emuc3/an1/v ref -/cn3/rb1 pgd3 /emud3/an0/v ref +/cn2/rb0 oc8/updn/cn16/rd7 pwm3l/re4 pwm2h/re3 pwm2l/re2 v ddcore pwm1l/re0 c1tx/rf1 pwm1h/re1 oc2/rd1 oc3/rd2 pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 av dd av ss u2cts /an8/rb8 an9/rb9 tms/an10/rb10 tdo/an11/rb11 v ss v dd tck/an12/rb12 tdi/an13/rb13 u2rts /an14/rb14 an15/ocfb/cn12/rb15 u2tx/scl2/cn18/rf5 u2rx / sda2/cn17/rf4 sda1/rg3 43 42 41 40 39 38 37 44 48 47 46 50 49 51 54 53 52 55 45 ss2 /t5ck/cn11/rg9 an5/qeb/ic8/cn7/rb5 an4/qea/ic7/cn6/rb4 ic3/int3/rd10 v dd c1rx/rf0 oc4/rd3 oc7/cn15/rd6 oc6/ic6/cn14/rd5 oc5/ic5/cn13/rd4 DSPIC33Fj128mc506 DSPIC33Fj64mc506 DSPIC33Fj128mc706
DSPIC33F/pic24h programming specification ds70152d-page 14 preliminary ? 2007 microchip technology inc. pin diagrams (continued) 80-pin tqfp 72 74 73 71 70 69 68 67 66 65 64 63 62 61 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 50 49 48 47 46 45 44 21 41 40 39 38 37 36 35 34 23 24 25 26 27 28 29 30 31 32 33 17 18 19 75 1 57 56 55 54 53 52 51 60 59 58 43 42 76 78 77 79 22 80 ic5/rd12 oc4/rd3 oc3/rd2 oc2/rd1 pwm2l/re2 pwm1h/re1 pwm1l/re0 crx2/rg0 c2tx/rg1 c1tx/rf1 c1rx/rf0 pwm3l/re4 pwm2h/re3 oc8/cn16/updn/rd7 oc6/cn14/rd5 oc1/rd0 ic4/rd11 ic2/rd9 ic1/rd8 ic3/rd10 v ss osc1/clkin/rc12 v dd scl1/rg2 u1rx/rf2 u1tx/rf3 pgc2 /emuc2/sosco/t1ck/cn0/rc14 pgd2 /emud2/sosci/cn1/rc13 v ref +/ra10 v ref -/ra9 av dd av ss u2cts /an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2rx/cn17/rf4 ic8/u1rts /cn21/rd15 u2tx/cn18/rf5 pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 pwm4h/re7 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr ss2 /cn11/rg9 an4/qea/cn6/rb4 an3/indx/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 pgc3 /emuc3/an1/cn3/rb1 pgd3 /emud3/an0/cn2/rb0 v ss v dd pwm3h/re5 pwm4l/re6 tdo/fltb/int2/re9 tms/flta/int1/re8 tck/an12/rb12 tdi/an13/rb13 u2rts /an14/rb14 an15/ocfb/cn12/rb15 v dd v ddcore oc5/cn13/rd4 ic6/cn19/rd13 sda1/rg3 sdi1/rf7 sdo1/rf8 an5/qeb/cn7/rb5 v ss osc2/clko/rc15 oc7/cn15/rd6 sck1/int0/rf6 ic7/u1cts /cn20/rd14 int4/ra3 int3/ra2 DSPIC33Fj64mc508
? 2007 microchip technology inc. preliminary ds70152d-page 15 DSPIC33F/pic24h prog ramming specification pin diagrams (continued) 80-pin tqfp 72 74 73 71 70 69 68 67 66 65 64 63 62 61 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 50 49 48 47 46 45 44 21 41 40 39 38 37 36 35 34 23 24 25 26 27 28 29 30 31 32 33 17 18 19 75 1 57 56 55 54 53 52 51 60 59 58 43 42 76 78 77 79 22 80 ic5/rd12 oc4/rd3 oc3/rd2 oc2/rd1 pwm2l/re2 pwm1h/re1 pwm1l/re0 crx2/rg0 c2tx/rg1 c1tx/rf1 c1rx/rf0 pwm3l/re4 pwm2h/re3 oc8/cn16/updn/rd7 oc6/cn14/rd5 oc1/rd0 ic4/rd11 ic2/rd9 ic1/rd8 ic3/rd10 v ss osc1/clkin/rc12 v dd scl1/rg2 u1rx/rf2 u1tx/rf3 pgc2 /emuc2/sosco/t1ck/cn0/rc14 pgd2 /emud2/sosci/cn1/rc13 v ref +/ra10 v ref -/ra9 av dd av ss u2cts /an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2rx/cn17/rf4 ic8/u1rts /cn21/rd15 u2tx/cn18/rf5 pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 pwm4h/re7 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr ss2 /cn11/rg9 an4/qea/cn6/rb4 an3/indx/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 pgc3 /emuc3/an1/cn3/rb1 pgd3 /emud3/an0/cn2/rb0 v ss v dd pwm3h/re5 pwm4l/re6 tdo/fltb/int2/re9 tms/flta/int1/re8 tck/an12/rb12 tdi/an13/rb13 u2rts /an14/rb14 an15/ocfb/cn12/rb15 v dd v ddcore oc5/cn13/rd4 ic6/cn19/rd13 sda1/rg3 sdi1/rf7 sdo1/rf8 an5/qeb/cn7/rb5 v ss osc2/clko/rc15 oc7/cn15/rd6 sck1/int0/rf6 ic7/u1cts /cn20/rd14 sda2/int4/ra3 scl2/int3/ra2 DSPIC33Fj128mc708
DSPIC33F/pic24h programming specification ds70152d-page 16 preliminary ? 2007 microchip technology inc. pin diagrams (continued) 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 26 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 95 1 76 77 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 96 98 97 99 27 46 47 48 49 50 55 54 53 52 51 100 oc6/cn14/rd5 oc5/cn13/rd4 ic6/cn19/rd13 ic5/rd12 oc4/rd3 oc3/rd2 oc2/rd1 an23/cn23/ra7 an22/cn22/ra6 pwm2l/re2 csdo/rg13 csdi/rg12 csck/rg14 pwm1h/re1 pwm1l/re0 rg0 pwm3l/re4 pwm2h/re3 c1rx/rf0 v ddcore pgd2 / emud2/sosci/cn1/rc13 oc1/rd0 ic3/rd10 ic2/rd9 ic1/rd8 ic4/rd11 ra3 ra2 osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 sck1/int0/rf6 sdi1/rf7 sdo1/rf8 sda1/rg3 u1rx/rf2 u1tx/rf3 v ss pgc2 / emuc2/sosco/t1ck/cn0/rc14 v ref +/ra10 v ref -/ra9 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2cts /rf12 u2rts /rf13 ic7/ u1cts /cn20/rd14 ic8/ u1rts /cn21/rd15 v dd v ss pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 u2tx/cn18/rf5 u2rx/cn17/rf4 pwm3h/re5 pwm4l/re6 pwm4h/re7 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 an18/t4ck/t9ck/rc3 an19/t5ck/t8ck/rc4 sck2/cn8/rg6 v dd tms/ra0 an20/flta/int1/re8 an21/fltb/int2/re9 an5/qeb/cn7/rb5 an4/qea/cn6/rb4 an3/indx/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 sdi2/cn9/rg7 sdo2/cn10/rg8 pgc3 /emuc3/ an1/cn3/rb1 pgd3 /emud3/ an0/cn2/rb0 cofs/rg15 v dd ss2 /cn11/rg9 mclr an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 rg1 c1tx/rf1 oc8/updn//cn16/rd7 oc7/cn15/rd6 tdo/ra5 int4/ra15 int3/ra14 v ss v ss v ss v dd tdi/ra4 tck/ra1 100-pin tqfp DSPIC33Fj64mc510
? 2007 microchip technology inc. preliminary ds70152d-page 17 DSPIC33F/pic24h prog ramming specification pin diagrams (continued) 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 26 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 95 1 76 77 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 96 98 97 99 27 46 47 48 49 50 55 54 53 52 51 100 oc6/cn14/rd5 oc5/cn13/rd4 ic6/cn19/rd13 ic5/rd12 oc4/rd3 oc3/rd2 oc2/rd1 an23/cn23/ra7 an22/cn22/ra6 pwm2l/re2 csdo/rg13 csdi/rg12 csck/rg14 pwm1h/re1 pwm1l/re0 rg0 pwm3l/re4 pwm2h/re3 c1rx/rf0 v ddcore pgd2 / emud2/sosci/cn1/rc13 oc1/rd0 ic3/rd10 ic2/rd9 ic1/rd8 ic4/rd11 sda2/ra3 scl2/ra2 osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 sck1/int0/rf6 sdi1/rf7 sdo1/rf8 sda1/rg3 u1rx/rf2 u1tx/rf3 v ss pgc2 / emuc2/sosco/t1ck/cn0/rc14 v ref +/ra10 v ref -/ra9 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2cts /rf12 u2rts /rf13 ic7/ u1cts /cn20/rd14 ic8/ u1rts /cn21/rd15 v dd v ss pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 u2tx/cn18/rf5 u2rx/cn17/rf4 pwm3h/re5 pwm4l/re6 pwm4h/re7 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 an18/t4ck/t9ck/rc3 an19/t5ck/t8ck/rc4 sck2/cn8/rg6 v dd tms/ra0 an20/flta/int1/re8 an21/fltb/int2/re9 an5/qeb/cn7/rb5 an4/qea/cn6/rb4 an3/indx/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 sdi2/cn9/rg7 sdo2/cn10/rg8 pgc3 /emuc3/ an1/cn3/rb1 pgd3 /emud3/ an0/cn2/rb0 cofs/rg15 v dd ss2 /cn11/rg9 mclr an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 rg1 c1tx/rf1 oc8/updn//cn16/rd7 oc7/cn15/rd6 tdo/ra5 int4/ra15 int3/ra14 v ss v ss v ss v dd tdi/ra4 tck/ra1 100-pin tqfp DSPIC33Fj128mc510 DSPIC33Fj256mc510
DSPIC33F/pic24h programming specification ds70152d-page 18 preliminary ? 2007 microchip technology inc. pin diagrams (continued) 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 26 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 95 1 76 77 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 96 98 97 99 27 46 47 48 49 50 55 54 53 52 51 100 oc6/cn14/rd5 oc5/cn13/rd4 ic6/cn19/rd13 ic5/rd12 oc4/rd3 oc3/rd2 oc2/rd1 an23/cn23/ra7 an22/cn22/ra6 pwm2l/re2 csdo/rg13 csdi/rg12 csck/rg14 pwm1h/re1 pwm1l/re0 c2rx/rg0 pwm3l/re4 pwm2h/re3 c1rx/rf0 v ddcore pgd2 / emud2/sosci/cn1/rc13 oc1/rd0 ic3/rd10 ic2/rd9 ic1/rd8 ic4/rd11 sda2/ra3 scl2/ra2 osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 sck1/int0/rf6 sdi1/rf7 sdo1/rf8 sda1/rg3 u1rx/rf2 u1tx/rf3 v ss pgc2 / emuc2/sosco/t1ck/cn0/rc14 v ref +/ra10 v ref -/ra9 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2cts /rf12 u2rts /rf13 ic7/ u1cts /cn20/rd14 ic8/ u1rts /cn21/rd15 v dd v ss pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 u2tx/cn18/rf5 u2rx/cn17/rf4 pwm3h/re5 pwm4l/re6 pwm4h/re7 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 an18/t4ck/t9ck/rc3 an19/t5ck/t8ck/rc4 sck2/cn8/rg6 v dd tms/ra0 an20/flta/int1/re8 an21/fltb/int2/re9 an5/qeb/cn7/rb5 an4/qea/cn6/rb4 an3/indx/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 sdi2/cn9/rg7 sdo2/cn10/rg8 pgc3 /emuc3/ an1/cn3/rb1 pgd3 /emud3/ an0/cn2/rb0 cofs/rg15 v dd ss2 /cn11/rg9 mclr an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 c2tx/rg1 c1tx/rf1 oc8/updn//cn16/rd7 oc7/cn15/rd6 tdo/ra5 int4/ra15 int3/ra14 v ss v ss v ss v dd tdi/ra4 tck/ra1 100-pin tqfp DSPIC33Fj64mc710 DSPIC33Fj128mc710 DSPIC33Fj256mc710
? 2007 microchip technology inc. preliminary ds70152d-page 19 DSPIC33F/pic24h prog ramming specification pin diagrams (continued) 64-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 36 35 34 33 32 31 30 29 28 27 26 64 63 62 61 60 59 58 57 56 14 15 16 17 18 19 20 21 22 23 24 25 pgc2 /emuc2/sosco/t1ck/cn0/rc14 pgd2 /emud2/sosci/t4ck/cn1/rc13 oc1/rd0 ic4/int4/rd11 ic2/u1cts /int2/rd9 ic1/int1/rd8 v ss osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 u1rts /sck1/int0/rf6 u1rx/sdi1/rf2 u1tx/sdo1/rf3 rg15 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr v ss v dd an3/cn5/rb3 an2/ss1 /cn4/rb2 pgc3 /emuc3/an1/v ref -/cn3/rb1 pgd3 /emud3/an0/v ref +/cn2/rb0 oc8/cn16/rd7 rg13 rg12 rg14 v ddcore rg1 rf1 rg0 oc2/rd1 oc3/rd2 pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 av dd av ss u2cts /an8/rb8 an9/rb9 tms/an10/rb10 tdo/an11/rb11 v ss v dd tck/an12/rb12 tdi/an13/rb13 u2rts /an14/rb14 an15/ocfb/cn12/rb15 u2tx/cn18/rf5 u2rx / cn17/rf4 sda1/rg3 43 42 41 40 39 38 37 44 48 47 46 50 49 51 54 53 52 55 45 ss2 /t5ck/cn11/rg9 an5/ic8/cn7/rb5 an4/ic7/cn6/rb4 ic3/int3/rd10 v dd rf0 oc4/rd3 oc7/cn15/rd6 oc6/ic6/cn14/rd5 oc5/ic5/cn13/rd4 pic24hj64gp206 pic24hj128gp206 pic24hj256gp206 note: the pic24hj64gp206 device does not have the scl2 and sda2 pins.
DSPIC33F/pic24h programming specification ds70152d-page 20 preliminary ? 2007 microchip technology inc. pin diagrams (continued) 64-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 36 35 34 33 32 31 30 29 28 27 26 64 63 62 61 60 59 58 57 56 14 15 16 17 18 19 20 21 22 23 24 25 pgc2 /emuc2/sosco/t1ck/cn0/rc14 pgd2 /emud2/sosci/t4ck/cn1/rc13 oc1/rd0 ic4/int4/rd11 ic2/u1cts /int2/rd9 ic1/int1/rd8 v ss osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 u1rts /sck1/int0/rf6 u1rx/sdi1/rf2 u1tx/sdo1/rf3 rg15 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr v ss v dd an3/cn5/rb3 an2/ss1 /cn4/rb2 pgc3 /emuc3/an1/v ref -/cn3/rb1 pgd3 /emud3/an0/v ref +/cn2/rb0 oc8/cn16/rd7 rg13 rg12 rg14 v ddcore rg1 rf1 rg0 oc2/rd1 oc3/rd2 pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 av dd av ss u2cts /an8/rb8 an9/rb9 tms/an10/rb10 tdo/an11/rb11 v ss v dd tck/an12/rb12 tdi/an13/rb13 u2rts /an14/rb14 an15/ocfb/cn12/rb15 u2tx/scl2/cn18/rf5 u2rx / sda2/cn17/rf4 sda1/rg3 43 42 41 40 39 38 37 44 48 47 46 50 49 51 54 53 52 55 45 ss2 /t5ck/cn11/rg9 an5/ic8/cn7/rb5 an4/ic7/cn6/rb4 ic3/int3/rd10 v dd rf0 oc4/rd3 oc7/cn15/rd6 oc6/ic6/cn14/rd5 oc5/ic5/cn13/rd4 pic24hj128gp306
? 2007 microchip technology inc. preliminary ds70152d-page 21 DSPIC33F/pic24h prog ramming specification pin diagrams (continued) 64-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 36 35 34 33 32 31 30 29 28 27 26 64 63 62 61 60 59 58 57 56 14 15 16 17 18 19 20 21 22 23 24 25 pgc2 /emuc2/sosco/t1ck/cn0/rc14 pgd2 /emud2/sosci/t4ck/cn1/rc13 oc1/rd0 ic4/int4/rd11 ic2/u1cts /int2/rd9 ic1/int1/rd8 v ss osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 u1rts /sck1/int0/rf6 u1rx/sdi1/rf2 u1tx/sdo1/rf3 cofs/rg15 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr v ss v dd an3/cn5/rb3 an2/ss1 /cn4/rb2 pgc3 /emuc3/an1/v ref -/cn3/rb1 pgd3 /emud3/an0/v ref +/cn2/rb0 oc8/cn16/rd7 csdo/rg13 csdi/rg12 csck/rg14 v ddcore rg1 c1tx/rf1 rg0 oc2/rd1 oc3/rd2 pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 av dd av ss u2cts /an8/rb8 an9/rb9 tms/an10/rb10 tdo/an11/rb11 v ss v dd tck/an12/rb12 tdi/an13/rb13 u2rts /an14/rb14 an15/ocfb/cn12/rb15 u2tx/scl2/cn18/rf5 u2rx / sda2/cn17/rf4 sda1/rg3 43 42 41 40 39 38 37 44 48 47 46 50 49 51 54 53 52 55 45 ss2 /t5ck/cn11/rg9 an5/ic8/cn7/rb5 an4/ic7/cn6/rb4 ic3/int3/rd10 v dd c1rx/rf0 oc4/rd3 oc7/cn15/rd6 oc6/ic6/cn14/rd5 oc5/ic5/cn13/rd4 pic24hj64gp506 pic24hj128gp506
DSPIC33F/pic24h programming specification ds70152d-page 22 preliminary ? 2007 microchip technology inc. pin diagrams (continued) 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 26 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 95 1 76 77 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 96 98 97 99 27 46 47 48 49 50 55 54 53 52 51 oc6/cn14/rd5 oc5/cn13/rd4 ic6/cn19/rd13 ic5/rd12 oc4/rd3 oc3/rd2 oc2/rd1 an23/cn23/ra7 an22/cn22/ra6 an26/re2 rg13 rg12 rg14 an25/re1 an24/re0 rg0 an28/re4 an27/re3 rf0 v ddcore pgd2 /emud2/sosci/cn1/rc13 oc1/rd0 ic3/rd10 ic2/rd9 ic1/rd8 ic4/rd11 sda2/ra3 scl2/ra2 osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 sck1/int0/rf6 sdi1/rf7 sdo1/rf8 sda1/rg3 u1rx/rf2 u1tx/rf3 v ss pgc2 /emuc2/sosco/t1ck/cn0/rc14 v ref +/ra10 v ref -/ra9 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2cts /rf12 u2rts /rf13 ic7/ u1cts /cn20/rd14 ic8/ u1rts /cn21/rd15 v dd v ss pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 u2tx/cn18/rf5 u2rx/cn17/rf4 an29/re5 an30/re6 an31/re7 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 an18/t4ck/t9ck/rc3 an19/t5ck/t8ck/rc4 sck2/cn8/rg6 v dd tms/ra0 an20/int1/ra12 an21/int2/ra13 an5/cn7/rb5 an4/cn6/rb4 an3/cn5/rb3 an2/ss1 /cn4/rb2 sdi2/cn9/rg7 sdo2/cn10/rg8 pgc3 /emuc3/an1/cn3/rb1 pgd3 /emud3/an0/cn2/rb0 rg15 v dd ss2 /cn11/rg9 mclr an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 rg1 rf1 oc8/cn16/rd7 oc7/cn15/rd6 tdo/ra5 int4/ra15 int3/ra14 v ss v ss v ss v dd tdi/ra4 tck/ra1 100-pin tqfp pic24hj64gp210 pic24hj128gp210 100 pic24hj128gp310 pic24hj256gp210
? 2007 microchip technology inc. preliminary ds70152d-page 23 DSPIC33F/pic24h prog ramming specification pin diagrams (continued) 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 26 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 95 1 76 77 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 96 98 97 99 27 46 47 48 49 50 55 54 53 52 51 oc6/cn14/rd5 oc5/cn13/rd4 ic6/cn19/rd13 ic5/rd12 oc4/rd3 oc3/rd2 oc2/rd1 an23/cn23/ra7 an22/cn22/ra6 an26/re2 rg13 rg12 rg14 an25/re1 an24/re0 rg0 an28/re4 an27/re3 c1rx/rf0 v ddcore pgd2 /emud2/sosci/cn1/rc13 oc1/rd0 ic3/rd10 ic2/rd9 ic1/rd8 ic4/rd11 sda2/ra3 scl2/ra2 osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 sck1/int0/rf6 sdi1/rf7 sdo1/rf8 sda1/rg3 u1rx/rf2 u1tx/rf3 v ss pgc2 /emuc2/sosco/t1ck/cn0/rc14 v ref +/ra10 v ref -/ra9 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2cts /rf12 u2rts /rf13 ic7/ u1cts /cn20/rd14 ic8/ u1rts /cn21/rd15 v dd v ss pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 u2tx/cn18/rf5 u2rx/cn17/rf4 an29/re5 an30/re6 an31/re7 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 an18/t4ck/t9ck/rc3 an19/t5ck/t8ck/rc4 sck2/cn8/rg6 v dd tms/ra0 an20/int1/ra12 an21/int2/ra13 an5/cn7/rb5 an4/cn6/rb4 an3/cn5/rb3 an2/ss1 /cn4/rb2 sdi2/cn9/rg7 sdo2/cn10/rg8 pgc3 /emuc3/an1/cn3/rb1 pgd3 /emud3/an0/cn2/rb0 rg15 v dd ss2 /cn11/rg9 mclr an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 rg1 c1tx/rf1 oc8/cn16/rd7 oc7/cn15/rd6 tdo/ra5 int4/ra15 int3/ra14 v ss v ss v ss v dd tdi/ra4 tck/ra1 100-pin tqfp pic24hj64gp510 100 pic24hj128gp510
DSPIC33F/pic24h programming specification ds70152d-page 24 preliminary ? 2007 microchip technology inc. pin diagrams (continued) 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 26 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 95 1 76 77 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 96 98 97 99 27 46 47 48 49 50 55 54 53 52 51 oc6/cn14/rd5 oc5/cn13/rd4 ic6/cn19/rd13 ic5/rd12 oc4/rd3 oc3/rd2 oc2/rd1 an23/cn23/ra7 an22/cn22/ra6 an26/re2 rg13 rg12 rg14 an25/re1 an24/re0 c2rx/rg0 an28/re4 an27/re3 c1rx/rf0 v ddcore pgd2 /emud2/sosci/cn1/rc13 oc1/rd0 ic3/rd10 ic2/rd9 ic1/rd8 ic4/rd11 sda2/ra3 scl2/ra2 osc2/clko/rc15 osc1/clkin/rc12 v dd scl1/rg2 sck1/int0/rf6 sdi1/rf7 sdo1/rf8 sda1/rg3 u1rx/rf2 u1tx/rf3 v ss pgc2 /emuc2/sosco/t1ck/cn0/rc14 v ref +/ra10 v ref -/ra9 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2cts /rf12 u2rts /rf13 ic7/ u1cts /cn20/rd14 ic8/ u1rts /cn21/rd15 v dd v ss pgc1 /emuc1/an6/ocfa/rb6 pgd1 /emud1/an7/rb7 u2tx/cn18/rf5 u2rx/cn17/rf4 an29/re5 an30/re6 an31/re7 an16/t2ck/t7ck/rc1 an17/t3ck/t6ck/rc2 an18/t4ck/t9ck/rc3 an19/t5ck/t8ck/rc4 sck2/cn8/rg6 v dd tms/ra0 an20/int1/ra12 an21/int2/ra13 an5/cn7/rb5 an4/cn6/rb4 an3/cn5/rb3 an2/ss1 /cn4/rb2 sdi2/cn9/rg7 sdo2/cn10/rg8 pgc3 /emuc3/an1/cn3/rb1 pgd3 /emud3/an0/cn2/rb0 rg15 v dd ss2 /cn11/rg9 mclr an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 c2tx/rg1 c1tx/rf1 oc8/cn16/rd7 oc7/cn15/rd6 tdo/ra5 int4/ra15 int3/ra14 v ss v ss v ss v dd tdi/ra4 tck/ra1 100-pin tqfp 100 pic24hj256gp610
? 2007 microchip technology inc. preliminary ds70152d-page 25 DSPIC33F/pic24h prog ramming specification pin diagrams (continued) 18-pin sdip 18-pin soic pgd2 /emud2/an0/vref+/cn2/ra0 pgc2 /emuc2/an1/vref-/cn3/ra1 int0/rp7/cn23/rb7 pgd3 /emud3/sosci/rp4/cn1/rb4 pgc3 /emuc3/sosco/t1ck/cn0/ra4 osco/clko/cn29/ra3 osci/clki/cn30/ra2 pgc1 /emuc1/an3/rp1/cn5/rb1 pgd1 /emud1/an2/rp0/cn4/rb0 an6/rp15/cn11/rb15 an7/rp14/cn12/rb14 scl1/rp9/cn21/rb9 sda1/rp8/cn22/rb8 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 v ss v ss v dd v ddcore mclr DSPIC33Fj12gp201 pic24hj12gp201
DSPIC33F/pic24h programming specification ds70152d-page 26 preliminary ? 2007 microchip technology inc. pin diagrams (continued) pin diagrams (continued) 20-pin sdip 20-pin ssop int0/rp7/cn23/rb7 mclr vss pwm1h1/rp14/cn12/rb14 v ddcore pwm2h1/scl1/rp8/cn22/rb8 pwm2l1/sda1/rp9/cn21/rb9 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 pgd2 /emud2/an0/vref+/cn2/ra0 pgc2 /emc2/an1/vref-/cn3/ra1 pgd1 /emud1/an2/rp0/cn4/rb0 pgc3 /emuc3/sosco/t1ck/cn0/ra4 osco/clko/cn29/ra3 osci/clki/cn30/ra2 pgd3 /emud3/sosci/rp4/cn1/rb4 pgc1 /emuc1/an3/rp1/cn5/rb1 pwm1l2/rp13/cn13/rb13 pwm1l1/rp15/cn11/rb15 pwm1h2/rp12/cn14/rb12 v dd v ss DSPIC33Fj12mc201 28-pin sdip 28-pin soic int0/rp7/cn23/rb7 mclr av ss an7/rp14/cn12/rb14 v ddcore ascl1/rp6/cn24/rb6 tdo/sda1/rp9/cn21/rb9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 an4/rp2/cn6/rb2 pgc3 /emuc3/sosco/t1ck/cn0/ra4 osci/clki/cn29/ra3 an5/rp3/cn7/rb3 pgd3 /emud3/sosc/rp4/cn1/rb4 av dd an8/rp13/cn13/rb13 an6/rp15/cn11/rb15 an9/rp12/cn14/rb12 asda1/rp5/cn27/rb5 vss osco/clk1/cn30/ra2 v dd tms/rp11/cn15/rb11 tdi/rp10/cn16/rb10 vss tck/scl1/rp8/cn22/rb8 pgd2 /emud2/an0/vref+/cn2/ra0 pgc2 /emuc2/an1/vref-/cn3/ra1 pgc1 /emuc1/an3/rp1/cn5/rb1 pgd1 /emud1/an2/rp0/cn4/rb0 DSPIC33Fj12gp202 pic24hj12gp202
? 2007 microchip technology inc. preliminary ds70152d-page 27 DSPIC33F/pic24h prog ramming specification pin diagrams (continued) 28-pin sdip 28-pin soic int0/rp7/cn23/rb7 mclr av ss pwm1h1/rp14/cn12/rb14 v ddcore ascl1/rp6/cn24/rb6 tdo/pwm2l1/sda1/rp9/cn21/rb9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 an5/rp3/cn7/rb3 pgd2 /emud2/an0/vref+/cn2/ra0 pgc2 /emuc2/an1/vref-/cn3/ra1 pgd1 /emud1/an2/rp0/cn4/rb0 pgc3 /emuc3/sosco/t1ck/cn0/ra4 osci/clki/cn30/ra2 an4/rp2/cn6/rb2 pgd3 /emud3/sosci/rp4/cn1/rb4 pgc1 /emuc1/an3/rp1/cn5/rb1 pwm1l2/rp13/cn13/rb13 pwm1l1/rp15/cn11/rb15 pwm1h2/rp12/cn14/rb12 asda1/rp5/cn27/rb5 vss osco/clko/cn29/ra3 v dd tms/pwm1l3/rp11/cn15/rb11 tdi/pwm1h3/rp10/cn16/rb10 vss tck/pwm2h1/scl1/rp8/cn22/rb8 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DSPIC33Fj12mc202 av dd
DSPIC33F/pic24h programming specification ds70152d-page 28 preliminary ? 2007 microchip technology inc. pin diagrams (continued) 28-pin qfn 6*6mm 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 v ss pgd1 / emud1 /an2/rp0/cn4/rb0 pgc1 / emuc1 /an3/rp1/cn5/rb1 an4/rp2/cn6/rb2 an5/rp3/cn7/rb3 osci/clki/cn30/ra2 osco/clko/cn29/ra3 v ddcore tdi/rp10/cn16/rb10 tms/rp11/cn15/rb11 an9/rp12/cn14/rb12 tdo/sda1/rp9/cn21/rb9 an8/rp13/cn13/rb13 pgc3 / emuc3 /sosco/t1ck/cn0/ra4 pgd3 / emud3 /sosci/rp4/cn1/rb4 v dd asda1/rp5/cn27/rb5 ascl1/rp6/cn24/rb6 int0/rp7/cn23/rb7 tck/scl1/rp8/cn22/rb8 pgd2 / emud2 /an0/vref+/cn2/ra0 pgc2 / emuc2 /an1/vref-/cn3/ra1 mclr an6/rp15/cn11/rb15 an7/rp14/cn12/rb14 v ss DSPIC33Fj12gp202 av ss av dd pic24hj12gp202
? 2007 microchip technology inc. preliminary ds70152d-page 29 DSPIC33F/pic24h prog ramming specification pin diagrams (continued) 28-pin qfn 6*6mm 1 2 3 4 5 6 7 21 20 19 18 17 16 15 8 9 10 11 12 13 14 DSPIC33Fj12mc202 pgd1 / emud1 /an2/rp0/cn4/rb0 pgc1 / emuc1 /an3/rp1/cn5/rb1 an4/rp2/cn6/rb2 an5/rp3/cn7/rb3 osci/clki/cn30/ra2 osco/clko/cn29/ra3 v ss v ddcore tdi/pwm1h3/rp10/cn16/rb10 tms/pwm1l3/rp11/cn15/rb11 pwm1h2/rp12/cn14/rb12 tdo/pwm2l1/sda1/rp9/cn21/rb9 pwm1l2/rp13/cn13/rb13 pgc3 / emuc3 /sosco/t1ck/cn0/ra4 pgd3 / emud3 /sosci/rp4/cn1/rb4 v dd asda1/rp5/cn27/rb5 ascl1/rp6/cn24/rb6 int0/rp7/cn23/rb7 tck/pwm2h1/scl1/rp8/cn22/rb8 pgc2 /emuc2/an1/vref-/cn3/ra1 pgd2 /emud2/an0/vref+/cn2/ra0 mclr av dd av ss pwm1l1/rp15/cn11/rb15 pwm1h1/ rp14/cn12/rb14 28 27 26 25 24 23 22 v ss
DSPIC33F/pic24h programming specification ds70152d-page 30 preliminary ? 2007 microchip technology inc. 2.4 memory map the program memory map extends from 0x0 to 0xfffffe. code storage is located at the base of the memory map and supports up to 88k instructions (about 256 kbytes). table 2-2 shows the program memory size and number of erase and program blocks present in each device variant. each erase block, or page, contains 512 instructions and each program block, or row, contains 64 instructions. locations 0x800000 through 0x800ffe are reserved for executive code memory. this region stores the programming executive and the debugging executive. the programming executive is used for device pro- gramming and the debug executive is used for in-circuit debugging. this region of memory can not be used to store user code. locations 0xf80000 through 0xf80017 are reserved for the device configuration registers. locations 0xff0000 and 0xff0002 are reserved for the device id word registers. these bits can be used by the programmer to identify what device type is being programmed. they are described in section 7.0 ?device id? . the device id registers read out normally, even after code protection is applied. figure 2-3 shows the memory map for the DSPIC33F/ pic24h family variants. table 2-2: code memory size DSPIC33F/pic24h device user memory address limit (instruction words) write blocks erase blocks executive memory address limit (instruction words) DSPIC33Fj64gp206 0x00abfe (22k) 344 43 0x800ffe (2k) DSPIC33Fj64gp306 0x00abfe (22k) 344 43 0x800ffe (2k) DSPIC33Fj64gp310 0x00abfe (22k) 344 43 0x800ffe (2k) DSPIC33Fj64gp706 0x00abfe (22k) 344 43 0x800ffe (2k) DSPIC33Fj64gp708 0x00abfe (22k) 344 43 0x800ffe (2k) DSPIC33Fj64gp710 0x00abfe (22k) 344 43 0x800ffe (2k) DSPIC33Fj128gp206 0x 0157fe (44k) 688 86 0x800ffe (2k) DSPIC33Fj128gp306 0x 0157fe (44k) 688 86 0x800ffe (2k) DSPIC33Fj128gp310 0x 0157fe (44k) 688 86 0x800ffe (2k) DSPIC33Fj128gp706 0x 0157fe (44k) 688 86 0x800ffe (2k) DSPIC33Fj128gp708 0x 0157fe (44k) 688 86 0x800ffe (2k) DSPIC33Fj128gp710 0x 0157fe (44k) 688 86 0x800ffe (2k) DSPIC33Fj256gp506 0x02abfe (88k) 1368 171 0x 800ffe (2k) DSPIC33Fj256gp510 0x02abfe (88k) 1368 171 0x 800ffe (2k) DSPIC33Fj256gp710 0x02abfe (88k) 1368 171 0x 800ffe (2k) DSPIC33Fj64mc506 0x00abfe (22k) 344 43 0x800ffe (2k) DSPIC33Fj64mc508 0x00abfe (22k) 344 43 0x800ffe (2k) DSPIC33Fj64mc510 0x00abfe (22k) 344 43 0x800ffe (2k) DSPIC33Fj64mc706 0x00abfe (22k) 344 43 0x800ffe (2k) DSPIC33Fj64mc710 0x00abfe (22k) 344 43 0x800ffe (2k) DSPIC33Fj128mc506 0x 0157fe (44k) 688 86 0x800ffe (2k) DSPIC33Fj128mc510 0x 0157fe (44k) 688 86 0x800ffe (2k) DSPIC33Fj128mc706 0x 0157fe (44k) 688 86 0x800ffe (2k) DSPIC33Fj128mc708 0x 0157fe (44k) 688 86 0x800ffe (2k) DSPIC33Fj128mc710 0x 0157fe (44k) 688 86 0x800ffe (2k) DSPIC33Fj256mc510 0x02abfe (88k) 1368 171 0x 800ffe (2k) DSPIC33Fj256mc710 0x02abfe (88k) 1368 171 0x 800ffe (2k) pic24hj64gp206 0x00abfe (22k) 344 43 0x800ffe (2k) pic24hj64gp210 0x00abfe (22k) 344 43 0x800ffe (2k) pic24hj64gp506 0x00abfe (22k) 344 43 0x800ffe (2k) pic24hj64gp510 0x00abfe (22k) 344 43 0x800ffe (2k) pic24hj128gp206 0x 0157fe (44k) 688 86 0x800ffe (2k) pic24hj128gp210 0x 0157fe (44k) 688 86 0x800ffe (2k)
? 2007 microchip technology inc. preliminary ds70152d-page 31 DSPIC33F/pic24h prog ramming specification pic24hj128gp306 0x 0157fe (44k) 688 86 0x800ffe (2k) pic24hj128gp310 0x 0157fe (44k) 688 86 0x800ffe (2k) pic24hj128gp506 0x 0157fe (44k) 688 86 0x800ffe (2k) pic24hj128gp510 0x 0157fe (44k) 688 86 0x800ffe (2k) pic24hj256gp206 0x02abfe (88k) 1368 171 0x800ffe (2k) pic24hj256gp210 0x02abfe (88k) 1368 171 0x800ffe (2k) pic24hj256gp610 0x02abfe (88k) 1368 171 0x800ffe (2k) DSPIC33Fj12gp201 0x001ffe (4k) 64 8 0x 8007fe (1k) DSPIC33Fj12gp202 0x001ffe (4k) 64 8 0x 8007fe (1k) DSPIC33Fj12mc201 0x001ffe (4k) 64 8 0x 8007fe (1k) DSPIC33Fj12mc202 0x001ffe (4k) 64 8 0x 8007fe (1k) pic24hj12gp201 0x001ffe (4k) 64 8 0x 8007fe (1k) pic24hj12gp202 0x001ffe (4k) 64 8 0x 8007fe (1k) table 2-2: code memory size (continued)
DSPIC33F/pic24h programming specification ds70152d-page 32 preliminary ? 2007 microchip technology inc. figure 2-3: program memory map user memory space 0x000000 configuration registers code memory 0x02ac00 0x02abfe configuration memory space (87552 x 24-bit) 0x800000 0xf80000 (12 x 8-bit) 0xf80017 0xf80018 device id 0xfefffe 0xff0000 0xfffffe reserved 0xf7fffe reserved 0x800ffe 0x801000 executive code memory 0x7ffffe reserved 0xff0002 0xff0004 reserved (2 x 16-bit) note: the address boundaries for user flash and ex ecutive code memory are device dependent. user flash (2048 x 24-bit)
? 2007 microchip technology inc. preliminary ds70152d-page 33 DSPIC33F/pic24h prog ramming specification 3.0 device programming ? enhanced icsp this section discusses programming the device through enhanced icsp and the programming execu- tive. the programming executive resides in executive memory (separate from code memory) and is executed when enhanced icsp programming mode is entered. the programming executive provides the mechanism for the programmer (host device) to program and verify the DSPIC33F/pic24h programming specification family devices using a simple command set and com- munication protocol. there are several basic functions provided by the programming executive: ? read memory ? erase memory ? program memory ? blank check ? read executive firmware revision the programming executive performs the low-level tasks required for erasing, programming and verifying a device. this allows the programmer to program the device by issuing the appropriate commands and data. table 3-1 summarizes the commands. a detailed description for each command is provided in section 4.2 ?programming executive commands? . table 3-1: command set summary the programming executive uses the device?s data ram for variable storage and program execution. after the programming executive has run, no assumptions should be made about the contents of data ram. 3.1 overview of the programming process figure 3-1 shows the high-level overview of the programming process. after entering enhanced icsp mode, the programming executive is verified. next, the device is erased. then, the code memory is pro- grammed, followed by the nonvolatile device configu- ration registers. code memory (including the configuration registers) is then verified to ensure that programming was successful. after the programming executive has been verified in memory (or loaded if not present), the DSPIC33F/ pic24h programming specification can be pro- grammed using the command set shown in table 3-1. figure 3-1: high-level enhanced icsp? programming flow command description scheck sanity check readc read configuration registers or device id registers readp read code memory progc program a configuration register and verify progp program one row of code memory and verify progw program one word of code memory and verify qblank query if the code memory is blank qver query the software version start done perform bulk erase program memory verify program enter enhanced icsp? program configuration bits verify configuration bits exit enhanced icsp
DSPIC33F/pic24h programming specification ds70152d-page 34 preliminary ? 2007 microchip technology inc. 3.2 confirming the presence of the programming executive before programming can begin, the programmer must confirm that the programming executive is stored in executive memory. the procedure for this task is shown in figure 3-2. first, icsp mode is entered. then, the unique applica- tion id word stored in executive memory is read. if the programming executive is resident, the application id word is 0xbb, which means programming can resume as normal. however, if the application id word is not 0xbb, the programming executive must be programmed to executive code memory using the method described in section 6.0 ?programming the programming exec- utive to memory? . section 5.0 ?device programming ? icsp? describes the icsp programming method. section 5.11 ?reading the application id word? describes the procedure for reading the application id word in icsp mode. figure 3-2: confirming presence of programming executive 3.3 entering enhanced icsp mode as shown in figure 3-3, entering enhanced icsp program/verify mode requires three steps: 1. the mclr pin is briefly driven high then low. 2. a 32-bit key sequence is clocked into pgd. 3. mclr is then driven high within a specified period of time and held. the programming voltage applied to mclr is v ih , which is essentially v dd in the case of DSPIC33F/ pic24h devices. there is no minimum time require- ment for holding at v ih . after v ih is removed, an inter- val of at least p18 must elapse before presenting the key sequence on pgd. the key sequence is a specific 32-bit pattern, ? 0100 1101 0100 0011 0100 1000 0101 0000 ? (more easily remembered as 0x4d434850 in hexa- decimal format). the device will enter program/verify mode only if the key sequence is valid. the most significant bit (msb) of the most significant nibble must be shifted in first. once the key sequence is complete, v ih must be applied to mclr and held at that level for as long as program/verify mode is to be maintained. an interval time of at least p19 and p7 must elapse before present- ing data on pgd. signals appearing on pgd before p7 has elapsed will not be interpreted as valid. on successful entry, the program memory can be accessed and programmed in serial fashion. while in the program/verify mode, all unused i/os are placed in the high-impedance state. is start enter icsp? mode application id 0xbb? resident in memory yes no prog. executive is application id read the be programmed prog. executive must from address 0x807f0 finish
? 2007 microchip technology inc. preliminary ds70152d-page 35 DSPIC33F/pic24h prog ramming specification figure 3-3: entering enhanced icsp? mode 3.4 blank check the term ?blank check? implies verifying that the device has been successfully erased and has no programmed memory locations. a blank or erased memory location is always read as a ? 1 ?. the device id registers (0xff0000:0xff0002) can be ignored by the blank check since this region stores device information that cannot be erased. the device configuration registers are also ignored by the blank check. additionally, all unimplemented memory space should be ignored from the blank check. the qblank command is used for the blank check. it determines if the code memory is erased by testing these memory regions. a ?blank? or ?not blank? response is returned. if it is determined that the device is not blank, it must be erased before attempting to program the chip. 3.5 code memory programming 3.5.1 programming methodology code memory is programmed with the progp command. progp programs one row of code memory starting from the memory address specified in the command. the number of progp commands required to program a device depends on the number of write blocks that must be programmed in the device. a flowchart for programming code memory is shown in figure 3-4. in this example, all 88k instruction words of a DSPIC33F/pic24h device are programmed. first, the number of commands to send (called ?remainingc- mds? in the flowchart) is set to 1368 and the destination address (called ?baseaddress?) is set to ? 0 ?. next, one write block in the device is programmed with a progp command. each progp command contains data for one row of code memory of the DSPIC33F/pic24h. after the first command is processed successfully, ?remainingcmds? is decremented by ? 1 ? and compared with ? 0 ?. since there are more progp commands to send, ?baseaddress? is incremented by 0x80 to point to the next row of memory. on the second progp command, the second row is programmed. this process is repeated until the entire device is programmed.. mclr pgd pgc v dd p6 p14 b31 b30 b29 b28 b27 b2 b1 b0 b3 ... program/verify entry code = 0x4d434850 p1a p1b p18 p19 01001 0000 p7 v ih v ih note: if a bootloader needs to be programmed, the bootloader code must not be pro- grammed into the first page of code mem- ory. for example, if a bootloader located at address 0x200 attempts to erase the first page, it would inadvertently erase itself. instead, program the bootloader into the second page, e.g. 0x400.
DSPIC33F/pic24h programming specification ds70152d-page 36 preliminary ? 2007 microchip technology inc. figure 3-4: flowchart for programming code memory 3.5.2 programming verification after code memory is programmed, the contents of memory can be verified to ensure that programming was successful. verification requires code memory to be read back and compared against the copy held in the programmer?s buffer. the readp command can be used to read back all the programmed code memory. alternatively, you can have the programmer perform the verification after the entire device is programmed, using a checksum computation. 3.5.3 checksum computation only the configuration registers are included in the checksum computation. the device id and unit id are not included in the checksum computation. table 3-2 shows how this 16-bit computation can be made for each DSPIC33F and pic24h device. compu- tations for read code protection are shown both enabled and disabled. the checksum values shown here assume that the configuration registers are also erased. however, when code protection is enabled, the value of the fgs register is assumed to be 0x5. is progp response pass? is remainingcmds ? 0 ?? baseaddress = 0x0 remainingcmds = 1368 remainingcmds = remainingcmds ? 1 baseaddress = baseaddress + 0x80 no no yes yes start failure report error send progp command to program baseaddress finish
? 2007 microchip technology inc. preliminary ds70152d-page 37 DSPIC33F/pic24h prog ramming specification table 3-2: checksum computation device read code protection checksum computation erased value value with 0xaaaaaa at 0x0 and last code address DSPIC33Fj64gp206 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj64gp306 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj64gp310 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj64gp706 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj64gp708 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj64gp710 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj128gp206 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba DSPIC33Fj128gp306 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba DSPIC33Fj128gp310 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba DSPIC33Fj128gp706 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba DSPIC33Fj128gp708 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba DSPIC33Fj128gp710 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba DSPIC33Fj256gp506 disabled cfgb + sum(0:02abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj256gp510 disabled cfgb + sum(0:02abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj256gp710 disabled cfgb + sum(0:02abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba item description: sum(a:b) = byte sum of locations a to b inclusive (all 3 bytes of code memory) cfgb = configuration block (masked) = byte sum of ((fbs & 0xcf) + (fss & 0xff) + (fgs & 0x07) + (foscsel & 0xa7) + (fosc & 0xe7) + (fwdt & 0xdf) + (fpor & 0xe7) + (ficd & 0xe3)) (for DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202) = byte sum of ((fbs & 0xcf) + (fss & 0xcf) + (fgs & 0x07) + (foscsel & 0xa7) + (fosc & 0xc7) + (fwdt & 0xdf) + (fpor & 0xe7) + (ficd & 0xe3)) (for all other devices)
DSPIC33F/pic24h programming specification ds70152d-page 38 preliminary ? 2007 microchip technology inc. DSPIC33Fj64mc506 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj64mc508 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj64mc510 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj64mc706 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj64mc710 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj128mc506 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba DSPIC33Fj128mc510 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba DSPIC33Fj128mc706 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba DSPIC33Fj128mc708 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba DSPIC33Fj128mc710 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba DSPIC33Fj256mc510 disabled cfgb + sum(0:02abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj256mc710 disabled cfgb + sum(0:02abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba pic24hj64gp206 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba pic24hj64gp210 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba pic24hj64gp506 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba table 3-2: checksum computation (continued) device read code protection checksum computation erased value value with 0xaaaaaa at 0x0 and last code address item description: sum(a:b) = byte sum of locations a to b inclusive (all 3 bytes of code memory) cfgb = configuration block (masked) = byte sum of ((fbs & 0xcf) + (fss & 0xff) + (fgs & 0x07) + (foscsel & 0xa7) + (fosc & 0xe7) + (fwdt & 0xdf) + (fpor & 0xe7) + (ficd & 0xe3)) (for DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202) = byte sum of ((fbs & 0xcf) + (fss & 0xcf) + (fgs & 0x07) + (foscsel & 0xa7) + (fosc & 0xc7) + (fwdt & 0xdf) + (fpor & 0xe7) + (ficd & 0xe3)) (for all other devices)
? 2007 microchip technology inc. preliminary ds70152d-page 39 DSPIC33F/pic24h prog ramming specification pic24hj64gp510 disabled cfgb + sum(0:00abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba pic24hj128gp206 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba pic24hj128gp210 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba pic24hj128gp306 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba pic24hj128gp310 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba pic24hj128gp506 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba pic24hj128gp510 disabled cfgb + sum(0:0157ff) 0x01bc 0xffbe enabled cfgb 0x05ba 0x05ba pic24hj256gp206 disabled cfgb + sum(0:02abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba pic24hj256gp210 disabled cfgb + sum(0:02abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba pic24hj256gp610 disabled cfgb + sum(0:02abff) 0x03bc 0x01be enabled cfgb 0x05ba 0x05ba DSPIC33Fj12gp201 disabled cfgb + sum(0:001fff) 0xd60c 0xd40e enabled cfgb 0x060a 0x060a DSPIC33Fj12gp202 disabled cfgb + sum(0:001fff) 0xd60c 0xd40e enabled cfgb 0x060a 0x060a DSPIC33Fj12mc201 disabled cfgb + sum(0:001fff) 0xd60c 0xd40e enabled cfgb 0x060a 0x060a DSPIC33Fj12mc202 disabled cfgb + sum(0:001fff) 0xd60c 0xd40e enabled cfgb 0x060a 0x060a pic24hj12gp201 disabled cfgb + sum(0:001fff) 0xd60c 0xd40e enabled cfgb 0x060a 0x060a pic24hj12gp202 disabled cfgb + sum(0:001fff) 0xd60c 0xd40e enabled cfgb 0x060a 0x060a table 3-2: checksum computation (continued) device read code protection checksum computation erased value value with 0xaaaaaa at 0x0 and last code address item description: sum(a:b) = byte sum of locations a to b inclusive (all 3 bytes of code memory) cfgb = configuration block (masked) = byte sum of ((fbs & 0xcf) + (fss & 0xff) + (fgs & 0x07) + (foscsel & 0xa7) + (fosc & 0xe7) + (fwdt & 0xdf) + (fpor & 0xe7) + (ficd & 0xe3)) (for DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202) = byte sum of ((fbs & 0xcf) + (fss & 0xcf) + (fgs & 0x07) + (foscsel & 0xa7) + (fosc & 0xc7) + (fwdt & 0xdf) + (fpor & 0xe7) + (ficd & 0xe3)) (for all other devices)
DSPIC33F/pic24h programming specification ds70152d-page 40 preliminary ? 2007 microchip technology inc. 3.6 configuration bits programming 3.6.1 overview the DSPIC33F/pic24h has configuration bits stored in twelve 8-bit configuration registers, aligned on even configuration memory address boundaries. these bits can be set or cleared to select various device configu- rations. there are three types of configuration bits: system operation bits, code-protect bits and unit id bits. the system operation bits determine the power-on set- tings for system level components, such as oscillator and watchdog timer. the code-protect bits prevent program memory from being read and written. the register descriptions for the fbs, fss, fgs, foscsel, fosc, fwdt, fpor and ficd configuration registers are shown in table 3-3. the configuration register map is shown in table 3-4.. note: if any of the code-protect bits in fbs, fss or fgs is clear, then the entire device must be erased before it can be reprogrammed.
? 2007 microchip technology inc. preliminary ds70152d-page 41 DSPIC33F/pic24h prog ramming specification table 3-3: DSPIC33F/pic24h configuration bits description bit field register description rbs<1:0> fbs boot segment data ram code protection 11 = no ram is reserved for boot segment 10 = small-sized boot ram [128 bytes of ram are reserved for boot segment] 01 = medium-sized boot ram [256 bytes of ram are reserved for boot segment] 00 = large-sized boot ram [1024 bytes of ram are reserved for boot segment] [ note: this bit is reserved in DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202.] bss<2:0> fbs boot segment program memory code protection 111 = no boot segment 110 = standard security, small-sized boot program flash [boot segment ends at 0x0003ff in DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202. boot segment ends at 0x0007ff in other all other devices.] 101 = standard security, medium-sized boot program flash [boot segment ends at 0x0007ff in DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202. boot segment ends at 0x001fff in all other devices.] 100 = standard security, large-sized boot program flash [boot segment ends at 0x000fff in DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202. boot segment ends at 0x003fff in all other devices.] 011 = no boot segment 010 = high security, small-sized boot program flash [reserved in DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202. boot segment ends at 0x0007ff in all other devices.] 001 = high security, medium-sized boot program flash [reserved in DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202. boot segment ends at 0x001fff in all other devices.] 000 = high security, large-sized boot program flash [reserved in DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202. boot segment ends at 0x003fff in all other devices.] bwrp fbs boot segment program memory write protection 1 = boot segment program memory is not write-protected 0 = boot program memory is write-protected
DSPIC33F/pic24h programming specification ds70152d-page 42 preliminary ? 2007 microchip technology inc. rss<1:0> fss secure segment data ram code protection 11 = no data ram is reserved for secure segment 10 = small-sized secure ram [(256 ? n) bytes of ram are reserved for secure segment in all other devices.] 01 = medium-sized secure ram [(2048 ? n) bytes of ram are reserved for secure segment in all other devices.] 00 = large-sized secure ram [(4096 ? n) bytes of ram are reserved for secure segment in all other devices.] where n = number of bytes of ram reserved for boot sector. note 1: this bit is reserved in DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202.] 2: if the defined boot segment size is greater than or equal to the defined secure segment, then the secure segment size selection has no effect and the secure segment is disabled. sss<2:0> fss secure segment program memory code protection 111 = no secure segment 110 = standard security, small-sized secure program flash [secure segment ends at 0x001fff for DSPIC33Fj64gpxxx/ DSPIC33Fj64mcxxx/pic24hj64gpxxx devices, and at 0x003fff in other devices.] 101 = standard security, medium-sized secure program flash [secure segment ends at 0x003fff for DSPIC33Fj64gpxxx/ DSPIC33Fj64mcxxx/pic24hj64gpxxx devices, and at 0x007fff in other devices.] 100 = standard security, large-sized secure program flash [secure segment ends at 0x007fff for DSPIC33Fj64gpxxx/ DSPIC33Fj64mcxxx/pic24hj64gpxxx devices, and at 0x00ffff in other devices.] 011 = no secure segment 010 = high security, small-sized secure program flash [secure segment ends at 0x001fff for DSPIC33Fj64gpxxx/ DSPIC33Fj64mcxxx/pic24hj64gpxxx devices, and at 0x003fff in other devices.] 001 = high security, medium-sized secure program flash [secure segment ends at 0x003fff for DSPIC33Fj64gpxxx/ DSPIC33Fj64mcxxx/pic24hj64gpxxx devices, and at 0x007fff in other devices.] 000 = high security, large-sized secure program flash [secure segment ends at 0x007fff for DSPIC33Fj64gpxxx/ DSPIC33Fj64mcxxx/pic24hj64gpxxx devices, and at 0x00ffff in other devices.] [ note: this bit is reserved in DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202.] swrp fss secure segment program memory write protection 1 = secure segment program memory is not write-protected 0 = secure program memory is write-protected [ note: this bit is reserved in DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202.] table 3-3: DSPIC33F/pic24h configuration bits description (continued) bit field register description
? 2007 microchip technology inc. preliminary ds70152d-page 43 DSPIC33F/pic24h prog ramming specification gss<1:0> fgs general segment code-protect bit 11 = code protection is disabled 10 = standard security code protection is enabled 0x = reserved in DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202. in all other devices, high security code protection is enabled. gwrp fgs general segment write-protect bit 1 = general segment program memory is not write-protected 0 = general segment program memory is write-protected ieso foscsel two-speed oscillator start-up enable bit 1 = start up device with frc, then automatically switch to the user-selected oscillator source when ready 0 = start up device with user-selected oscillator source temp foscsel temperature protection enable bit 1 = temperature protection disabled 0 = temperature protection enabled fnosc<2:0> foscsel initial oscillator source selection bits 111 = internal fast rc (frc) oscillator 110 = reserved 101 = lprc oscillator 100 = secondary (lp) oscillator 011 = primary (xt, hs, ec) oscillator with pll 010 = primary (xt, hs, ec) oscillator 001 = internal fast rc (frc) oscillator with pll 000 = reserved fcksm<1:0> fosc clock switching mode bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled iol1way fosc peripheral pin select configuration 1 = allow only one reconfiguration 0 = allow multiple reconfigurations [ note: this bit is only present in the DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202 devices.] osciofnc fosc osc2 pin function bit (except in xt and hs modes) 1 = osc2 is clock output 0 = osc2 is general purpose digital i/o pin poscmd<1:0> fosc primary oscillator mode select bits 11 = primary oscillator disabled 10 = hs crystal oscillator mode 01 = xt crystal oscillator mode 00 = ec (external clock) mode fwdten fwdt watchdog enable bit 1 = watchdog always enabled (lprc oscillator cannot be disabled. clearing the swdten bit in the rcon register will have no effect) 0 = watchdog enabled/disabled by user software (lprc can be disabled by clearing the swdten bit in the rcon register) windis fwdt watchdog timer window enable bit 1 = watchdog timer in non-window mode 0 = watchdog timer in window mode wdtpre fwdt watchdog timer prescaler bit 1 = 1:128 0 = 1:32 table 3-3: DSPIC33F/pic24h configuration bits description (continued) bit field register description
DSPIC33F/pic24h programming specification ds70152d-page 44 preliminary ? 2007 microchip technology inc. wdtpost fwdt watchdog timer postscaler bits 1111 = 1:32,768 1110 = 1:16,384 . . . 0001 = 1:2 0000 = 1:1 pwmpin fpor motor control pwm module pin mode 1 = pwm module pins controlled by port register at device reset (tri-stated) 0 = pwm module pins controlled by pwm module at device reset (configured as output pins) hpol fpor motor control pwm high-side polarity bit 1 = pwm module high-side output pins have active-high output polarity 0 = pwm module high-side output pins have active-low output polarity lpol fpor motor control pwm low-side polarity bit 1 = pwm module low-side output pins have active-high output polarity 0 = pwm module low-side output pins have active-low output polarity alti2c fpor alternate i 2 c? pins 1 = i 2 c mapped to sda1/scl1 pins 0 = i 2 c mapped to asda1/sacl1 pins [ note: this bit is only present in the DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202 devices.] fpwrt<2:0> fpor power-on reset timer value select bits 111 = pwrt = 128 ms 110 = pwrt = 64 ms 101 = pwrt = 32 ms 100 = pwrt = 16 ms 011 = pwrt = 8 ms 010 = pwrt = 4 ms 001 = pwrt = 2 ms 000 = pwrt disabled bkbug ficd background debug enable bit 1 = device will reset in user mode 0 = device will reset in debug mode coe ficd debugger/emulator enable bit 1 = device will reset in operational mode 0 = device will reset in clip-on emulation mode jtagen ficd jtag enable bit 1 = jtag enabled 0 = jtag disabled ics<1:0> ficd icd communication channel select bits 11 = communicate on pgc1/emuc1 and pgd1/emud1 10 = communicate on pgc2/emuc2 and pgd2/emud2 01 = communicate on pgc3/emuc3 and pgd3/emud3 00 = reserved, do not use ? all unimplemented (read as ? 0 ?, write as ? 0 ?) table 3-3: DSPIC33F/pic24h configuration bits description (continued) bit field register description
? 2007 microchip technology inc. preliminary ds70152d-page 45 DSPIC33F/pic24h prog ramming specification table 3-4: DSPIC33F/pic24h device configuration register map note 1: on the DSPIC33F general purpose family devices (DSPIC33Fjxxxgpxxx) and pic24h devices, these bits are reserved (read as ? 1 ? and must be programmed as ? 1 ?). 2: these bits are only present in the DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202 devices. in all other devices, they are unimplemented (read as ? 0 ?). 3: in the DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202 devices, these bits are reserved (read as ? 1 ? and must be programmed as ? 1 ?). 3.6.2 programming methodology configuration bits may be programmed a single byte at a time using the progc command. this command specifies the configuration data and configuration register address. when configuration bits are programmed, any unimplemented bits must be programmed with a ? 0 ? and any reserved bits must be programmed with a ? 1 ?. twelve progc commands are required to program all the configuration bits. a flowchart for configuration bit programming is shown in figure 3-5. 3.6.3 programming verification after the configuration bits are programmed, the contents of memory should be verified to ensure that the programming was successful. verification requires the configuration bits to be read back and compared against the copy held in the programmer?s buffer. the readc command reads back the programmed configuration bits and verifies that the programming was successful. any unimplemented configuration bits are read-only and read as ? 0 ?. the reserved bits are read-only and read as ? 1 ?. 3.6.4 codeguard security configuration bits the fbs, fss and fgs configuration registers are special configuration registers that control the size and level of code protection for the boot segment, secure segment and general segment, respectively. for each segment, two main forms of code protection are provided. one form prevents code memory from being written (write protection), while the other prevents code memory from being read (read protection). bwrp, swrp and gwrp bits control write protection and bss<2:0>, sss<2:0> and gss<1:0> bits controls read protection. the chip erase eraseb command sets all the code protection bits to ? 1 ?, which allows the device to be programmed. when write protection is enabled, any programming operation to code memory will fail. when read protec- tion is enabled, any read from code memory will cause a ?0x0? to be read, regardless of the actual contents of code memory. since the programming executive always verifies what it programs, attempting to program code memory with read protection enabled will also result in failure. it is imperative that all code protection bits are ? 1 ? while the device is being programmed and verified. only after the device is programmed and verified should any of the above bits be programmed to ? 0 ?. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0xf80000 fbs rbs<1:0> (3) ? bss<2:0> bwrp 0xf80002 fss rss<1:0> (3) ? sss<2:0> (3) swrp (3) 0xf80004 fgs ? gss<1:0> gwrp 0xf80006 foscsel ieso ? temp ? fnosc<2:0> 0xf80008 fosc fcksm<1:0> iol1way (2) ? osciofnc poscmd<1:0> 0xf8000a fwdt fwdten windis - wdtpre wdtpost<3:0> 0xf8000c fpor pwmpin (1) hpol (1) lpol (1) alti2c (2) ?fpwrt<2:0> 0xf8000e ficd bkbug coe jtagen ? ics<1:0> 0xf80010 fuid0 user unit id byte 0 0xf80012 fuid1 user unit id byte 1 0xf80014 fuid2 user unit id byte 2 0xf80016 fuid3 user unit id byte 3 note: if the general code segment code- protect bit (gcp) is programmed to ? 0 ?, code memory is code-protected and can not be read. code memory must be verified before enabling read protec- tion. see section 3.6.4 ?codeguard security configuration bits? for more information about code-protect configura- tion bits.
DSPIC33F/pic24h programming specification ds70152d-page 46 preliminary ? 2007 microchip technology inc. in addition to code memory protection, a part of data ram can be configured to be accessible only by code resident in the boot segment and/or secure segment. the sizes of these ?reserved? sections are user-config- urable, using the rbs<1:0> and rss<1:0> bits. 3.6.5 user unit id the DSPIC33F/pic24h devices provide four 8-bit con- figuration registers (fuid0 through fuid3) for the user to store product-specific information, such as unit serial numbers and other product manufacturing data. figure 3-5: configuratio n bit programming flow 3.7 exiting enhanced icsp mode exiting program/verify mode is done by removing v ih from mclr , as shown in figure 3-6. the only require- ment for exit is that an interval p16 should elapse between the last clock and program signals on pgc and pgd before removing v ih . figure 3-6: exiting enhanced icsp? mode note: all bits in the fbs, fss and fgs configu- ration registers can only be programmed to a value of ? 0 ?. the eraseb command is the only way to reprogram code-protect bits from on (? 0 ?) to off (? 1 ?). send progc command configaddress = 0xf80000 is progc response pass? no yes no failure report error start finish yes is configaddress 0xf80018? configaddress = configaddress + 2 mclr p16 pgd pgd = input pgc v dd v ih v ih p17
? 2007 microchip technology inc. preliminary ds70152d-page 47 DSPIC33F/pic24h prog ramming specification 4.0 the programming executive 4.1 programming executive communication the programmer and programming executive have a master-slave relationship, where the programmer is the master programming device and the programming executive is the slave. all communication is initiated by the programmer in the form of a command. only one command at a time can be sent to the programming executive. in turn, the programming executive only sends one response to the programmer after receiving and processing a command. the programming executive command set is described in section 4.2 ?programming executive commands? . the response set is described in section 4.3 ?programming executive responses? . 4.1.1 communication interface and protocol the icsp/enhanced icsp interface is a 2 wire spi implemented using the pgc and pgd pins. the pgc pin is used as a clock input pin and the clock source must be provided by the programmer. the pgd pin is used for sending command data to and receiving response data from the programming executive. all serial data is transmitted on the falling edge of pgc and latched on the rising edge of pgc. all data trans- missions are sent to the most significant bit (msb) first using 16-bit mode (see figure 4-1). figure 4-1: programming executive serial timing since a 2 wire spi is used, and data transmissions are bidirectional, a simple protocol is used to control the direction of pgd. when the programmer completes a command transmission, it releases the pgd line and allows the programming executive to drive this line high. the programming executive keeps the pgd line high to indicate that it is processing the command. after the programming executive has processed the command, it brings pgd low for 15 sec to indicate to the programmer that the response is available to be clocked out. the programmer can begin to clock out the response 23 sec after pgd is brought low and it must provide the necessary amount of clock pulses to receive the entire response from the programming executive. after the entire response is clocked out, the program- mer should terminate the clock on pgc until it is time to send another command to the programming executive. this protocol is shown in figure 4-2. 4.1.2 spi rate in enhanced icsp mode, the DSPIC33F/pic24h family devices operate from the fast internal rc oscillator, which has a nominal frequency of 7.3728 mhz. this oscillator frequency yields an effective system clock frequency of 1.8432 mhz. to ensure that the program- mer does not clock too fast, it is recommended that a 7.35 mhz clock be provided by the programmer. 4.1.3 time outs the programming executive uses no watchdog or time out for transmitting responses to the programmer. if the programmer does not follow the flow control mechanism using pgc as described in section 4.1.1 ?communication interface and protocol? , it is possible that the programming executive will behave unexpectedly while trying to send a response to the programmer. since the programming executive has no time out, it is imperative that the programmer correctly follow the described communication protocol. as a safety measure, the programmer should use the command time outs identified in table 4-1. if the command time out expires, the programmer should reset the programming executive and start programming the device again. pgc pgd 123 11 13 15 16 14 12 lsb 14 13 12 11 45 6 msb 1 2 3 ... 4 5 p2 p3 p1 p1b p1a
DSPIC33F/pic24h programming specification ds70152d-page 48 preliminary ? 2007 microchip technology inc. figure 4-2: programming executive ? programmer communication protocol 4.2 programming executive commands the programming executive command set is shown in table 4-1. this table contains the opcode, mnemonic, length, time out and description for each command. functional details on each command are provided in the command descriptions ( section 4.2.4 ?command descriptions? ). 4.2.1 command format all programming executive commands have a general format consisting of a 16-bit header and any required data for the command (see figure 4-3). the 16-bit header consists of a 4-bit opcode field, which is used to identify the command, followed by a 12-bit command length field. figure 4-3: command format the command opcode must match one of those in the command set. any command that is received which does not match the list in table 4-1 will return a ?nack? response (see section 5.3.1.1 ?opcode field? ). the command length is represented in 16-bit words since the spi operates in 16-bit mode. the program- ming executive uses the command length field to determine the number of words to read from the spi port. if the value of this field is incorrect, the command will not be properly received by the programming executive. 4.2.2 packed data format when 24-bit instruction words are transferred across the 16-bit spi interface, they are packed to conserve space using the format shown in figure 4-4. this format minimizes traffic over the spi and provides the programming executive with data that is properly aligned for performing table write operations. figure 4-4: packed instruction word format 4.2.3 programming executive error handling the programming executive will ?nack? all unsupported commands. additionally, due to the memory constraints of the programming executive, no checking is performed on the data contained in the programmer command. it is the responsibility of the programmer to command the programming executive with valid command arguments or the programming operation may fail. additional information on error handling is provided in section 5.3.1.3 ?qe_code field? . 1 2 15 16 1 2 15 16 pgc pgd pgc = input pgc = input (idle) host transmits last command word pgd = input pgd = output p8 12 1516 msb x x x lsb msb x x x lsb msb x x x lsb 1 0 p9b pgc = input pgd = output p9a programming executive processes command host clocks out response 8ns 23 s 15 12 11 0 opcode length command data first word (if required) ? ? command data last word (if required) note: when the number of instruction words transferred is odd, msb2 is zero and lsw2 can not be transmitted. 15 8 7 0 lsw1 msb2 msb1 lsw2 lswx: least significant 16 bits of instruction word msbx: most significant byte of instruction word
? 2007 microchip technology inc. preliminary ds70152d-page 49 DSPIC33F/pic24h prog ramming specification table 4-1: programming executive command set 4.2.4 command descriptions all commands supported by the programming executive are described in section 5.2.5 ?scheck command? through section 4.2.12 ?qver command? . 4.2.5 scheck command the scheck command instructs the programming executive to do nothing but generate a response. this command is used as a ?sanity check? to verify that the programming executive is operational. expected response (2 words): 0x1000 0x0002 opcode mnemonic length (16-bit words) time out description 0x0 scheck 1 1 msec sanity check. 0x1 readc 3 1 msec read an 8-bit word from the specified configuration register or device id register. 0x2 readp 4 1 msec/row read ?n? 24-bit instruction words of code memory starting from the specified address. 0x3 reserved n/a n/a this command is reserved. it will return a nack. 0x4 progc 4 5 msec write an 8-bit word to the specified configuration register. 0x5 progp 99 5 msec program one row of code memory at the specified address, then verify. 0x6 progw 5 5 msec program one instruction word of code memory at the specified address, then verify. 0x7 reserved n/a n/a this command is reserved. it will return a nack. 0x8 reserved n/a n/a this command is reserved. it will return a nack. 0x9 reserved n/a n/a this command is reserved. it will return a nack. 0xa qblank 2 tbd query if the code memory is blank. 0xb qver 1 1 msec query the programming executive software version. 0xc reserved n/a n/a this command is reserved. it will return a nack. 0xd reserved n/a n/a this command is reserved. it will return a nack. legend: tbd = to be determined note: one row of code memory consists of (64) 24-bit word s. refer to table 2-2 for device-specific information. 15 12 11 0 opcode length field description opcode 0x0 length 0x1 note: this instruction is not required for programming, but is provided for development purposes only.
DSPIC33F/pic24h programming specification ds70152d-page 50 preliminary ? 2007 microchip technology inc. 4.2.6 readc command the readc command instructs the programming exec- utive to read n configuration registers or device id registers, starting from the 24-bit address specified by addr_msb and addr_ls. this command can only be used to read 8-bit or 16-bit data. when this command is used to read configuration registers, the upper byte in every data word returned by the programming executive is 0x00 and the lower byte contains the configuration register value. expected response (4 + 3 * (n ? 1)/2 words for n odd): 0x1100 2 + n configuration register or device id register 1 ... configuration register or device id register n 4.2.7 readp command the readp command instructs the programming exec- utive to read n 24-bit words of code memory, starting from the 24-bit address specified by addr_msb and addr_ls. this command can only be used to read 24- bit data. all data returned in the response to this com- mand uses the packed data format described in section 4.2.2 ?packed data format? . expected response (2 + 3 * n/2 words for n even): 0x1200 2 + 3 * n/2 least significant program memory word 1 ... least significant data word n expected response (4 + 3 * (n ? 1)/2 words for n odd): 0x1200 4 + 3 * (n ? 1)/2 least significant program memory word 1 ... msb of program memory word n (zero padded) 15 12 11 8 7 0 opcode length naddr_msb addr_ls field description opcode 0x1 length 0x3 n number of 8-bit conf iguration registers or device id registers to read (max of 256) addr_msb msb of 24-bit source address addr_ls least significant 16 bits of 24-bit source address note: reading unimplemented memory will cause the programming executive to reset. please ensure that only memory locations present on a particular device are accessed. 15 12 11 8 7 0 opcode length n reserved addr_msb addr_ls field description opcode 0x2 length 0x4 n number of 24-bit instructions to read (max of 32768) reserved 0x0 addr_msb msb of 24-bit source address addr_ls least significant 16 bits of 24-bit source address note: reading unimplemented memory will cause the programming executive to reset. please ensure that only memory locations present on a particular device are accessed.
? 2007 microchip technology inc. preliminary ds70152d-page 51 DSPIC33F/pic24h prog ramming specification 4.2.8 progc command the progc command instructs the programming exec- utive to program a single configuration register, located at the specified memory address. after the specified data word has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. expected response (2 words): 0x1400 0x0002 4.2.9 progp command the progp command instructs the programming exec- utive to program one row of code memory (64 instruction words) to the specified memory address. programming begins with the row address specified in the command. the destination address should be a multiple of 0x80. the data to program to memory, located in command words d_1 through d_96, must be arranged using the packed instruction word format shown in figure 4-4. after all data has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. expected response (2 words): 0x1500 0x0002 15 12 11 8 7 0 opcode length reserved addr_msb addr_ls data field description opcode 0x4 length 0x4 reserved 0x0 addr_msb msb of 24-bit destination address addr_ls least significant 16 bits of 24-bit destination address data 8-bit data word 15 12 11 8 7 0 opcode length reserved addr_msb addr_ls d_1 d_2 ... d_n field description opcode 0x5 length 0x63 reserved 0x0 addr_msb msb of 24-bit destination address addr_ls least significant 16 bits of 24-bit destination address d_1 16-bit data word 1 d_2 16-bit data word 2 ... 16-bit data word 3 through 95 d_96 16-bit data word 96 note: refer to table 2-2 for code memory size information.
DSPIC33F/pic24h programming specification ds70152d-page 52 preliminary ? 2007 microchip technology inc. 4.2.10 progw command the progw command instructs the programming exec- utive to program one word of code memory (3 bytes) to the specified memory address. after the word has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. expected response (2 words): 0x1600 0x0002 4.2.11 qblank command the qblank command queries the programming exec- utive to determine if the contents of code memory are blank (contains all ? 1 ?s). the size of code memory to check must be specified in the command. the blank check for code memory begins at 0x0 and advances toward larger addresses for the specified number of instruction words. qblank returns a qe_code of 0xf0 if the specified code memory and code-protect bits are blank; otherwise, qblank returns a qe_code of 0x0f. expected response (2 words for blank device): 0x1af0 0x0002 expected response (2 words for non-blank device): 0x1a0f 0x0002 15 12 11 8 7 0 opcode length reserved addr_msb addr_ls data_ls reserved data_msb field description opcode 0x6 length 0x5 reserved 0x0 addr_msb msb of 24-bit destination address addr_ls least significant 16 bits of 24-bit destination address data_msb msb of 24-bit data data_ls least significant 16 bits of 24-bit data 15 12 11 0 opcode length psize field description opcode 0xa length 0x2 psize length of program memory to check (in 24-bit words) +1, up to a max of 49152 note: the qblank command does not check the system operation configuration bits since these bits are not set to ? 1 ? when a chip erase is performed.
? 2007 microchip technology inc. preliminary ds70152d-page 53 DSPIC33F/pic24h prog ramming specification 4.2.12 qver command the qver command queries the version of the programming executive software stored in test memory. the ?version.revision? information is returned in the response?s qe_code using a single byte with the following format: main version in upper nibble and revision in the lower nibble (i.e., 0x23 means version 2.3 of programming executive software). expected response (2 words): 0x1bmn (where ?mn? stands for version m.n) 0x0002 4.3 programming executive responses the programming executive sends a response to the programmer for each command that it receives. the response indicates if the command was processed correctly. it includes any required response data or error data. the programming executive response set is shown in table 4-2. this table contains the opcode, mnemonic and description for each response. the response format is described in section 4.3.1 ?response format? . table 4-2: programming executive response opcodes 4.3.1 response format all programming executive responses have a general format consisting of a two-word header and any required data for the command. 4.3.1.1 opcode field the opcode is a 4-bit field in the first word of the response. the opcode indicates how the command was processed (see table 4-2). if the command was processed successfully, the response opcode is pass. if there was an error in processing the command, the response opcode is fail and the qe_code indicates the reason for the failure. if the command sent to the programming executive is not identified, the programming executive returns a nack response. 4.3.1.2 last_cmd field the last_cmd is a 4-bit field in the first word of the response and indicates the command that the programming executive processed. since the program- ming executive can only process one command at a time, this field is technically not required. however, it can be used to verify that the programming executive correctly received the command that the programmer transmitted. 15 12 11 0 opcode length field description opcode 0xb length 0x1 opcode mnemonic description 0x1 pass command successfully processed. 0x2 fail command unsuccessfully processed. 0x3 nack command not known. field description opcode response opcode. last_cmd programmer command that generated the response. qe_code query code or error code. length response length in 16-bit words (includes 2 header words). d_1 first 16-bit data word (if applicable). d_n last 16-bit data word (if applicable). 15 12 11 8 7 0 opcode last_cmd qe_code length d_1 (if applicable) ... d_n (if applicable)
DSPIC33F/pic24h programming specification ds70152d-page 54 preliminary ? 2007 microchip technology inc. 4.3.1.3 qe_code field the qe_code is a byte in the first word of the response. this byte is used to return data for query commands and error codes for all other commands. when the programming executive processes one of the two query commands ( qblank or qver ), the returned opcode is always pass and the qe_code holds the query response data. the format of the qe_code for both queries is shown in table 4-3. table 4-3: qe_code for queries when the programming executive processes any command other than a query, the qe_code repre- sents an error code. supported error codes are shown in table 4-4. if a command is successfully processed, the returned qe_code is set to 0x0, which indicates that there was no error in the command processing. if the verify of the programming for the progp or progc command fails, the qe_code is set to 0x1. for all other programming executive errors, the qe_code is 0x2. table 4-4: qe_code for non-query commands 4.3.1.4 response length the response length indicates the length of the programming executive?s response in 16-bit words. this field includes the 2 words of the response header. with the exception of the response for the readp command, the length of each response is only 2 words. the response to the readp command uses the packed instruction word format described in section 4.2.2 ?packed data format? . when reading an odd number of program memory words (n odd), the response to the readp command is (3 * (n + 1) / 2 + 2) words. when reading an even number of program memory words (n even), the response to the readp command is (3 * n / 2 + 2) words. query qe_code qblank 0x0f = code memory is not blank 0xf0 = code memory is blank qver 0xmn, where programming executive software version = m.n (i.e., 0x32 means software version 3.2). qe_code description 0x0 no error. 0x1 verify failed. 0x2 other error.
? 2007 microchip technology inc. preliminary ds70152d-page 55 DSPIC33F/pic24h prog ramming specification 5.0 device programming ? icsp icsp mode is a special programming protocol that allows you to read and write to DSPIC33F/pic24h device family memory. the icsp mode is the most direct method used to program the device; note, how- ever, that enhanced icsp is faster. icsp mode also has the ability to read the contents of executive mem- ory to determine if the programming executive is present. this capability is accomplished by applying control codes and instructions serially to the device using pins pgc and pgd. in icsp mode, the system clock is taken from the pgc pin, regardless of the device?s oscillator configuration bits. all instructions are shifted serially into an internal buffer, then loaded into the instruction register and executed. no program fetching occurs from internal memory. instructions are fed in 24 bits at a time. pgd is used to shift data in, and pgc is used as both the serial shift clock and the cpu execution clock. 5.1 overview of the programming process figure 5-1 shows the high-level overview of the programming process. after entering icsp mode, the first action is to bulk erase the device. next, the code memory is programmed, followed by the device con- figuration registers. code memory (including the configuration registers) is then verified to ensure that programming was successful. then, program the code-protect configuration bits, if required. figure 5-1: high-level icsp? programming flow 5.2 icsp operation upon entry into icsp mode, the cpu is idle. execution of the cpu is governed by an internal state machine. a 4-bit control code is clocked in using pgc and pgd and this control code is used to command the cpu (see table 5-1). the six control code is used to send instructions to the cpu for execution and the regout control code is used to read data out of the device via the visi register. table 5-1: cpu control codes in icsp? mode note: during icsp operation, the operating frequency of pgc must not exceed 5mhz. 4-bit control code mnemonic description 0000b six shift in 24-bit instruction and execute. 0001b regout shift out the visi register. 0010b-1111b n/a reserved. start perform bulk erase program memory verify program done enter icsp? program configuration bits verify configuration bits exit icsp
DSPIC33F/pic24h programming specification ds70152d-page 56 preliminary ? 2007 microchip technology inc. 5.2.1 six serial instruction execution the six control code allows execution of DSPIC33F/ pic24h programming specification assembly instruc- tions. when the six code is received, the cpu is sus- pended for 24 clock cycles, as the instruction is then clocked into the internal buffer. once the instruction is shifted in, the state machine allows it to be executed over the next four clock cycles. while the received instruction is executed, the state machine simultaneously shifts in the next 4-bit command (see figure 5-2). 5.2.2 regout serial instruction execution the regout control code allows for data to be extracted from the device in icsp mode. it is used to clock the contents of the visi register out of the device over the pgd pin. after the regout control code is received, the cpu is held idle for 8 cycles. after these eight cycles, an additional 16 cycles are required to clock the data out (see figure 5-3). the regout code is unique because the pgd pin is an input when the control code is transmitted to the device. however, after the control code is processed, the pgd pin becomes an output as the visi register is shifted out. figure 5-2: six serial execution figure 5-3: regout serial execution note 1: coming out of reset, the first 4-bit control code is always forced to six and a forced nop instruction is executed by the cpu. five additional pgc clocks are needed on start-up, thereby resulting in a 9-bit six command instead of the normal 4-bit six command. after the forced six is clocked in, icsp operation resumes as normal (the next 24 clock cycles load the first instruction word to the cpu). 2: tblrdh , tblrdl , tblwth and tblwtl instructions must be followed by a nop instruction. note: data is transmitted on the falling edge and latched on the rising edge of pgc. for all data transmissions, the least significant bit (lsb) is transmitted first. p4 23 12 3 2324 1 2 3 4 p1 pgc p4a pgd 24-bit instruction fetch execute 24-bit instruction , execute pc ? 1, 14 0000 fetch six control code fetch next control code 45678 1819202122 17 lsb x x x x x x x x x x x x x x msb pgd = input p2 p3 p1b p1a 56 7 0000 000 only for program memory entry 89 00 1234 1278 pgc p4 pgd pgd = input execute previous instruction, cpu held in idle shift out visi register<15:0> p5 pgd = output 123 1234 p4a 11 13 15 16 14 12 no execution takes place, fetch next control code 0 000 0 pgd = input msb 1 2 3 4 1 45 6 lsb 14 13 12 ... 11 10 0 fetch regout control code 0
? 2007 microchip technology inc. preliminary ds70152d-page 57 DSPIC33F/pic24h prog ramming specification 5.3 entering icsp mode as shown in figure 5-4, entering icsp program/verify mode requires three steps: 1. mclr is briefly driven high then low. 2. a 32-bit key sequence is clocked into pgd. 3. mclr is then driven high within a specified period of time and held. the programming voltage applied to mclr is v ih , which is essentially v dd in the case of DSPIC33F/ pic24h devices. there is no minimum time require- ment for holding at v ih . after v ih is removed, an inter- val of at least p18 must elapse before presenting the key sequence on pgd. the key sequence is a specific 32-bit pattern, ? 0100 1101 0100 0011 0100 1000 0101 0001 ? (more easily remembered as 0x4d434851 in hexa- decimal). the device will enter program/verify mode only if the sequence is valid. the most significant bit (msb) of the most significant nibble must be shifted in first. once the key sequence is complete, v ih must be applied to mclr and held at that level for as long as program/verify mode is to be maintained. an interval of at least time p19 and p7 must elapse before presenting data on pgd. signals appearing on pgd before p7 has elapsed will not be interpreted as valid. on successful entry, the program memory can be accessed and programmed in serial fashion. while in icsp mode, all unused i/os are placed in the high-impedance state. figure 5-4: entering icsp? mode 5.4 flash memory programming in icsp mode 5.4.1 programming operations flash memory write and erase operations are controlled by the nvmcon register. programming is performed by setting nvmcon to select the type of erase operation (table 5-2) or write operation (table 5-3) and initiating the programming by setting the wr control bit (nvmcon<15>). in icsp mode, all programming operations are self- timed. there is an internal delay between the user set- ting the wr control bit and the automatic clearing of the wr control bit when the programming operation is complete. please refer to section table 8-1: ?ac/ dc characteristics and timing requirements? for information about the delays associated with various programming operations. table 5-2: nvmcon erase operations mclr pgd pgc v dd p6 p14 b31 b30 b29 b28 b27 b2 b1 b0 b3 ... program/verify entry code = 0x4d434851 p1a p1b p18 p19 01001 0001 p7 v ih v ih nvmcon value erase operation 0x404f erase all code memory, executive memory and configuration registers (does not erase unit id or device id registers). 0x404d erase general segment and fgs configuration register. 0x404c erase secure segment and fss configuration register. this operation will also erase the general segment and fgs configuration register. 0x4042 erase a page of code memory or executive memory. 0x4040 erase a configuration register byte.
DSPIC33F/pic24h programming specification ds70152d-page 58 preliminary ? 2007 microchip technology inc. table 5-3: nvmcon write operations 5.4.2 starting and stopping a programming cycle the wr bit (nvmcon<15>) is used to start an erase or write cycle. setting the wr bit initiates the programming cycle. all erase and write cycles are self-timed. the wr bit should be polled to determine if the erase or write cycle has been completed. starting a programming cycle is performed as follows: bset nvmcon, #wr 5.5 erasing program memory the procedure for erasing program memory (all of code memory, data memory, executive memory and code- protect bits) consists of setting nvmcon to 0x404f and then executing the programming cycle. for seg- ment erase operations, the nvmcon value should be modified suitably, according to table 5-2. figure 5-5 shows the icsp programming process for bulk erasing program memory. this process includes the icsp command code, which must be transmitted (for each instruction) least significant bit first, using the pgc and pgd pins (see figure 5-2). figure 5-5: bulk erase flow if a segment erase operation is required, step 3 must be modified with the appropriate nvmcon value as per table 5-2. the ability to individually erase various segments is a critical component of the codeguard? security fea- tures on DSPIC33F/pic24h devices. an individual code segment may be erased without affecting other segments. in addition, the configuration register corre- sponding to the erased code segment also gets erased. for example, the user might want to erase the code in the general segment without erasing a boot loader located in boot segment. the secure segment erase command is used to erase the secure segment and the fss configuration regis- ter. the general segment erase command is used to erase the general segment and the fgs configuration register. this command is only effective if a boot segment or secure segment has been enabled. before performing any segment erase operation, the programmer must first determine if the DSPIC33F/ pic24h device has defined a boot segment or secure segment, and ensure that a segment does not get overwritten by operations on any other segment. also, a bulk erase should not be performed if a boot segment or secure segment has been defined. the bss bit field in the fbs configuration register can be read to determine whether a boot segment has been defined. if a boot segment has already been defined (and probably already been programmed), the user must be warned about this fact. similarly, the sss bit field in the fss configuration register can be read to determine whether a secure segment has been defined. if a secure segment has already been defined (and probably already been programmed), the user must be warned about this fact. a bulk erase operation is the recommended mecha- nism to allow a user to overwrite the boot segment (if one chooses to do so). in general, the segments and codeguard security- related configuration registers should be programmed in the following order: ? fbs and boot segment ? fss and secure segment ? fgs and general segment nvmcon value write operation 0x4001 program 1 row (64 instruction words) of code memory or executive memory. 0x4000 write a configuration register byte. 0x4003 program a code memory word. note: program memory must be erased before writing any data to program memory. start done set the wr bit to initiate erase write 0x404f to nvmcon sfr delay p11 + p10 time note 1: the boot segment and fbs configura- tion register can only be erased using a bulk erase. 2: a secure segment erase operation also erases the general segment and fgs configuration register. this is true even if secure segment is present on a device but not enabled.
? 2007 microchip technology inc. preliminary ds70152d-page 59 DSPIC33F/pic24h prog ramming specification table 5-4: serial instruction execution for bulk erasing code memory 5.6 writing code memory the procedure for writing code memory is similar to the procedure for writing the configuration registers, except that 64 instruction words are programmed at a time. to facilitate this operation, working registers, w0:w5, are used as temporary holding registers for the data to be programmed. table 5-5 shows the icsp programming details, includ- ing the serial pattern with the icsp command code, which must be transmitted least significant bit first using the pgc and pgd pins (see figure 5-2). in step 1, the reset vector is exited. in step 2, the nvmcon register is initialized for programming of code memory. in step 3, the 24-bit starting destination address for programming is loaded into the tblpag register and w7 register. the upper byte of the starting destination address is stored in tblpag and the lower 16 bits of the destination address are stored in w7. to minimize the programming time, the same packed instruction format that the programming executive uses is utilized (figure 4-4). in step 4, four packed instruc- tion words are stored in working registers, w0:w5, using the mov instruction and the read pointer, w6, is initialized. the contents of w0:w5 holding the packed instruction word data are shown in figure 5-6. in step 5, eight tblwt instructions are used to copy the data from w0:w5 to the write latches of code memory. since code memory is programmed 64 instruction words at a time, steps 4 and 5 are repeated 16 times to load all the write latches (step 6). after the write latches are loaded, programming is initiated by writing to the nvmcon register in steps 7 and 8. in step 9, the internal pc is reset to 0x200. this is a precautionary measure to prevent the pc from incre- menting into unimplemented memory when large devices are being programmed. lastly, in step 10, steps 3-9 are repeated until all of code memory is programmed. figure 5-6: packed instruction words in w0:w5 command (binary) data (hex) description step 1: exit the reset vector. 0000 0000 0000 0000 000000 000000 040200 000000 nop nop goto 0x200 nop step 2: set the nvmcon to erase all program memory. 0000 0000 2404fa 883b0a mov #0x404f, w10 mov w10, nvmcon step 3: initiate the erase cycle. 0000 0000 0000 a8e761 000000 000000 bset nvmcon, #wr nop nop step 4: wait for bulk erase operation to complete and make sure wr bit is clear. - 0000 0000 0000 0001 - 807600 887840 000000 externally time ?p11? msec (see section table 8-1: ?ac/dc characteristics and timing requirements? ) to allow suffi- cient time for the bulk erase operation to complete. mov nvmcon, w0 mov w0, visi nop clock out contents of visi register. repeat until the wr bit is clear. 15 8 7 0 w0 lsw0 w1 msb1 msb0 w2 lsw1 w3 lsw2 w4 msb3 msb2 w5 lsw3
DSPIC33F/pic24h programming specification ds70152d-page 60 preliminary ? 2007 microchip technology inc. table 5-5: serial instruction execution for writing code memory command (binary) data (hex) description step 1: exit the reset vector. 0000 0000 0000 0000 000000 000000 040200 000000 nop nop goto 0x200 nop step 2: set the nvmcon to program 64 instruction words. 0000 0000 24001a 883b0a mov #0x4001, w10 mov w10, nvmcon step 3: initialize the write pointer (w7) for tblwt instruction. 0000 0000 0000 200xx0 880190 2xxxx7 mov #, w0 mov w0, tblpag mov #, w7 step 4: initialize the read pointer (w6) and load w0:w5 with the next 4 instruction words to program. 0000 0000 0000 0000 0000 0000 2xxxx0 2xxxx1 2xxxx2 2xxxx3 2xxxx4 2xxxx5 mov #, w0 mov #, w1 mov #, w2 mov #, w3 mov #, w4 mov #, w5 step 5: set the read pointer (w6) and load the (next set of) write latches. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 eb0300 000000 bb0bb6 000000 000000 bbdbb6 000000 000000 bbebb6 000000 000000 bb1bb6 000000 000000 bb0bb6 000000 000000 bbdbb6 000000 000000 bbebb6 000000 000000 bb1bb6 000000 000000 clr w6 nop tblwtl [w6++], [w7] nop nop tblwth.b[w6++], [w7++] nop nop tblwth.b[w6++], [++w7] nop nop tblwtl [w6++], [w7++] nop nop tblwtl [w6++], [w7] nop nop tblwth.b[w6++], [w7++] nop nop tblwth.b[w6++], [++w7] nop nop tblwtl [w6++], [w7++] nop nop step 6: repeat steps 4-5 sixteen times to load the write latches for 64 instructions. step 7: initiate the write cycle. 0000 0000 0000 a8e761 000000 000000 bset nvmcon, #wr nop nop step 8: wait for row program operation to complete and make sure wr bit is clear.
? 2007 microchip technology inc. preliminary ds70152d-page 61 DSPIC33F/pic24h prog ramming specification figure 5-7: program code memory flow - 0000 0000 0000 0001 - 807600 887840 000000 externally time ?p13? msec (see section table 8-1: ?ac/dc characteristics and timing requirements? ) to allow suffi- cient time for the row program operation to complete. mov nvmcon, w0 mov w0, visi nop clock out contents of visi register. repeat until the wr bit is clear. step 9: reset device internal pc. 0000 0000 040200 000000 goto 0x200 nop step 10: repeat steps 3-9 until all code memory is programmed. table 5-5: serial instruction execution for writing code memory (continued) command (binary) data (hex) description start write sequence all locations done? no done start yes load 2 bytes to write buffer at all bytes written? no yes and poll for wr bit to be cleared n = 1 loopcount = 0 configure device for writes n = 1 loopcount = loopcount + 1 n = n + 1
DSPIC33F/pic24h programming specification ds70152d-page 62 preliminary ? 2007 microchip technology inc. 5.7 writing configuration memory the 8-bit configuration regi sters are programmable, one register at a time. the default programming values rec- ommended for the configuration registers are shown in table 5-6 and table 5-7. the recommended default foscsel value is 0x07, which selects the frc clock oscillator setting. the fbs, fss and fgs configuration registers are special since they enable code protection for the device. for security purposes, once any bit in these registers is programmed to ? 0 ? (to enable code protec- tion), it can only be set back to ? 1 ? by performing a bulk erase as described in section 5.5 ?erasing program memory? . programming any of these bits from a ? 0 ? to ? 1 ? is not possible, but they may be programmed from a ? 1 ? to a ? 0 ? to enable code protection. table 5-8 shows the icsp programming details for clear- ing the configuration registers. in step 1, the reset vec- tor is exited. in step 2, the write pointer (w7) is loaded with 0x0000, which is the original destination address (in tblpag, 0xf8 of program memory). in step 3, the nvmcon is set to program one configuration register. in step 4, the tblpag register is initialized to 0xf8 for writing to the configuration registers. in step 5, the value to write to each configuration register is loaded to w0. in step 6, the configuration register data is written to the write latch using the tblwtl instruction. in steps 7 and 8, the programming cycle is initiated. in step 9, the inter- nal pc is set to 0x200 as a safety measure to prevent the pc from incrementing into unimplemented memory. lastly, steps 4-9 are repeated until all twelve configuration registers are written. table 5-6: default configuration register values for DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/202 and pic24hj12gp201/202 table 5-7: default configuration register values for all other devices address name default value 0xf80000 fbs 0xcf 0xf80002 fss 0xff 0xf80004 fgs 0x07 0xf80006 foscsel 0xa7 0xf80008 fosc 0xe7 0xf8000a fwdt 0xdf 0xf8000c fpor 0xf7 0xf8000e ficd 0xe3 0xf80010 fuid0 0xff 0xf80012 fuid1 0xff 0xf80014 fuid2 0xff 0xf80016 fuid3 0xff address name default value 0xf80000 fbs 0xcf 0xf80002 fss 0xcf 0xf80004 fgs 0x07 0xf80006 foscsel 0xa7 0xf80008 fosc 0xc7 0xf8000a fwdt 0xdf 0xf8000c fpor 0xe7 0xf8000e ficd 0xe3 0xf80010 fuid0 0xff 0xf80012 fuid1 0xff 0xf80014 fuid2 0xff 0xf80016 fuid3 0xff
? 2007 microchip technology inc. preliminary ds70152d-page 63 DSPIC33F/pic24h prog ramming specification table 5-8: serial instruction execution for writing configuration registers command (binary) data (hex) description step 1: exit the reset vector. 0000 0000 0000 0000 000000 000000 040200 000000 nop nop goto 0x200 nop step 2: initialize the write pointer (w7) for the tblwt instruction. 0000 200007 mov #0x0000, w7 step 3: set the nvmcon register to program one configuration register. 0000 0000 24000a 883b0a mov #0x4000, w10 mov w10, nvmcon step 4: initialize the tblpag register. 0000 0000 200f80 880190 mov #0xf8, w0 mov w0, tblpag step 5: load the configuration register data to w6. 0000 2xxxx0 mov #, w0 step 6: write the configuration register data to the write latch and increment the write pointer. 0000 0000 0000 bb1b96 000000 000000 tblwtl w0, [w7++] nop nop step 7: initiate the write cycle. 0000 0000 0000 a8e761 000000 000000 bset nvmcon, #wr nop nop step 8: wait for the configuration register write operation to complete and make sure wr bit is clear. - 0000 0000 0000 0001 - 807600 887840 000000 externally time ?p20? msec (see section table 8-1: ?ac/dc characteristics and timing requirements? ) to allow suffi- cient time for the configuration register write operation to complete. mov, nvmcon, w0 mov w0, visi nop clock out contents of visi register. repeat until the wr bit is clear. step 9: reset device internal pc. 0000 0000 040200 000000 goto 0x200 nop step 10: repeat steps 5-9 until all twelve configuration registers are written.
DSPIC33F/pic24h programming specification ds70152d-page 64 preliminary ? 2007 microchip technology inc. 5.8 reading code memory reading from code memory is performed by executing a series of tblrd instructions and clocking out the data using the regout command. table 5-9 shows the icsp programming details for reading code memory. in step 1, the reset vector is exited. in step 2, the 24-bit starting source address for reading is loaded into the tblpag register and w6 register. the upper byte of the starting source address is stored in tblpag and the lower 16 bits of the source address are stored in w6. to minimize the reading time, the packed instruction word format that was utilized for writing is also used for reading (see figure 5-6). in step 3, the write pointer, w7, is initialized. in step 4, two instruction words are read from code memory and clocked out of the device, through the visi register, using the regout command. step 4 is repeated until the desired amount of code memory is read. table 5-9: serial instruction execution for reading code memory command (binary) data (hex) description step 1: exit reset vector. 0000 0000 0000 0000 000000 000000 040200 000000 nop nop goto 0x200 nop step 2: initialize tblpag and the read pointer (w6) for tblrd instruction. 0000 0000 0000 200xx0 880190 2xxxx6 mov #, w0 mov w0, tblpag mov #, w6 step 3: initialize the write pointer (w7) to point to the visi register. 0000 0000 207847 000000 mov #visi, w7 nop step 4: read and clock out the contents of the next two locations of code memory, through the visi register, using the regout command. 0000 0000 0000 0001 0000 0000 0000 0001 ba1b96 000000 000000 ba9bb6 000000 000000 tblrdl [w6], [w7] nop nop clock out contents of visi register tblrdh [w6++], [w7] nop nop clock out contents of visi register step 5: repeat step 4 until all desired code memory is read. step 6: reset device internal pc. 0000 0000 040200 000000 goto 0x200 nop
? 2007 microchip technology inc. preliminary ds70152d-page 65 DSPIC33F/pic24h prog ramming specification 5.9 reading configuration memory the procedure for reading configuration memory is similar to the procedure for reading code memory, except that 16-bit data words are read (with the upper byte read being all ? 0 ?s) instead of 24-bit words. since there are twelve configuration registers, they are read one register at a time. table 5-10 shows the icsp programming details for reading all of configuration memory. note that the tblpag register is hard coded to 0xf8 (the upper byte address of configuration memory) and the read pointer, w6, is initialized to 0x0000. table 5-10: serial instruction execution for reading all configuration memory command (binary) data (hex) description step 1: exit reset vector. 0000 0000 0000 0000 000000 000000 040200 000000 nop nop goto 0x200 nop step 2: initialize tblpag, the read pointer (w6) and the write pointer (w7) for tblrd instruction. 0000 0000 0000 0000 0000 200f80 880190 eb0300 207847 000000 mov #0xf8, w0 mov w0, tblpag clr w6 mov #visi, w7 nop step 3: read the configuration register and write it to the visi register (located at 0x784) and clock out the visi register using the regout command. 0000 0000 0000 0001 ba0bb6 000000 000000 tblrdl [w6++], [w7] nop nop clock out contents of visi register step 4: repeat step 3 twelve times to read all the configuration registers. step 5: reset device internal pc. 0000 0000 040200 000000 goto 0x200 nop
DSPIC33F/pic24h programming specification ds70152d-page 66 preliminary ? 2007 microchip technology inc. 5.10 verify code memory and configuration word the verify step involves reading back the code memory space and comparing it against the copy held in the programmer?s buffer. the configuration registers are verified with the rest of the code. the verify process is shown in the flowchart in figure 5-8. memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer?s buffer. refer to section 5.8 ?reading code memory? for implementation details of reading code memory. figure 5-8: verify code memory flow 5.11 reading the application id word the application id word is stored at address 0x8007f0 in executive code memory. to read this memory location, you must use the six control code to move this program memory location to the visi register. then, the regout control code must be used to clock the contents of the visi register out of the device. the corresponding control and instruction codes that must be serially transmitted to the device to perform this operation are shown in table 5-11. after the programmer has clocked out the application id word, it must be inspected. if the application id has the value 0xbb, the programming executive is resident in memory and the device can be programmed using the mechanism described in section 3.0 ?device programming ? enhanced icsp? . however, if the application id has any other value, the programming executive is not resident in memory; it must be loaded to memory before the device can be programmed. the procedure for loading the programming executive to memory is described in section 6.0 ?programming the programming executive to memory? . 5.12 exiting icsp mode exiting program/verify mode is done by removing v ih from mclr , as shown in figure 5-9. the only require- ment for exit is that an interval p16 should elapse between the last clock and program signals on pgc and pgd before removing v ih . figure 5-9: exiting icsp? mode note: because the configuration registers include the device code protection bit, code memory should be verified immedi- ately after writing if code protection is enabled. this is because the device will not be readable or verifiable if a device reset occurs after the code-protect bit in the fgs configuration register has been cleared. read low byte read high byte does word = expect data? failure, report error all code memory verified? no yes no set tblptr = 0 start yes done with post-increment with post-increment mclr p16 pgd pgd = input pgc v dd v ih v ih p17
? 2007 microchip technology inc. preliminary ds70152d-page 67 DSPIC33F/pic24h prog ramming specification table 5-11: serial instruction execution for reading the application id word command (binary) data (hex) description step 1: exit reset vector. 0000 0000 0000 0000 000000 000000 040200 000000 nop nop goto 0x200 nop step 2: initialize tblpag and the read pointer (w0) for tblrd instruction. 0000 0000 0000 0000 0000 0000 0000 0000 200800 880190 205fe0 207841 000000 ba0890 000000 000000 mov #0x80, w0 mov w0, tblpag mov #0x5be, w0 mov #visi, w1 nop tblrdl [w0], [w1] nop nop step 3: output the visi register using the regout command. 0001 clock out contents of the visi register
DSPIC33F/pic24h programming specification ds70152d-page 68 preliminary ? 2007 microchip technology inc. 6.0 programming the programming executive to memory 6.1 overview if it is determined that the programming executive is not present in executive memory (as described in section 3.2 ?confirming the presence of the pro- gramming executive? ), it must be programmed into executive memory using icsp, as described in section 5.0 ?device programming ? icsp? . storing the programming executive to executive memory is similar to normal programming of code memory. namely, the executive memory must first be erased, and then the programming executive must be programmed 64 words at a time. this control flow is summarized in table 6-1. table 6-1: programming the programming executive command (binary) data (hex) description step 1: exit reset vector and erase executive memory. 0000 0000 0000 0000 000000 000000 040200 000000 nop nop goto 0x200 nop step 2: initialize the nvmcon to erase a page of executive memory. 0000 0000 24072a 883b0a mov #0x4042, w10 mov w10, nvmcon step 3: initiate the erase cycle, wait for erase to complete and make sure wr bit is clear. 0000 0000 0000 - 0000 0000 0000 0001 a8e761 000000 000000 - 807600 887840 000000 bset nvmcon, #15 nop nop externally time ?p12? msec (see section table 8-1: ?ac/dc characteristics and timing requirements? ) to allow suffi- cient time for the page erase operation to complete. mov nvmcon, w0 mov w0, visi nop clock out contents of visi register. repeat until the wr bit is clear. step 4: repeat step 3 four times to erase all four pages of executive memory. step 5: initialize the nvmcon to program 64 instruction words. 0000 0000 24001a 883b0a mov #0x4001, w10 mov w10, nvmcon step 6: initialize tblpag and the write pointer (w7). 0000 0000 0000 0000 200800 880190 eb0380 000000 mov #0x80, w0 mov w0, tblpag clr w7 nop
? 2007 microchip technology inc. preliminary ds70152d-page 69 DSPIC33F/pic24h prog ramming specification step 7: load w0:w5 with the next 4 words of packed programming executive code and initialize w6 for programming. programming starts from the base of executive memory (0x800000) using w6 as a read pointer and w7 as a write pointer. 0000 0000 0000 0000 0000 0000 20 21 22 23 24 25 mov #, w0 mov #, w1 mov #, w2 mov #, w3 mov #, w4 mov #, w5 step 8: set the read pointer (w6) and load the (next four write) latches. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 eb0300 000000 bb0bb6 000000 000000 bbdbb6 000000 000000 bbebb6 000000 000000 bb1bb6 000000 000000 bb0bb6 000000 000000 bbdbb6 000000 000000 bbebb6 000000 000000 bb1bb6 000000 000000 clr w6 nop tblwtl [w6++], [w7] nop nop tblwth.b[w6++], [w7++] nop nop tblwth.b[w6++], [++w7] nop nop tblwtl [w6++], [w7++] nop nop tblwtl [w6++], [w7] nop nop tblwth.b[w6++], [w7++] nop nop tblwth.b[w6++], [++w7] nop nop tblwtl [w6++], [w7++] nop nop step 9: repeat steps 7-8 sixteen times to load the write latches for the 64 instructions. step 10: initiate the programming cycle. 0000 0000 0000 a8e761 000000 000000 bset nvmcon, #15 nop nop step 11: wait for the row program operation to complete. - 0000 0000 0000 0001 - 807600 887840 000000 externally time ?p13? msec (see section table 8-1: ?ac/dc characteristics and timing requirements? ) to allow suffi- cient time for the page erase operation to complete. mov nvmcon, w0 mov w0, visi nop clock out contents of visi register. repeat until the wr bit is clear. table 6-1: programming the programming executive (continued) command (binary) data (hex) description
DSPIC33F/pic24h programming specification ds70152d-page 70 preliminary ? 2007 microchip technology inc. step 12: reset the device internal pc. 0000 0000 040200 000000 goto 0x200 nop step 13: repeat steps 7-12 until all 32 rows of executive memory have been programmed. table 6-1: programming the programming executive (continued) command (binary) data (hex) description
? 2007 microchip technology inc. preliminary ds70152d-page 71 DSPIC33F/pic24h prog ramming specification 6.2 programming verification after the programming executive has been programmed to executive memory using icsp, it must be verified. verification is performed by reading out the contents of executive memory and comparing it with the image of the programming executive stored in the programmer. reading the contents of executive memory can be performed using the same technique described in section 5.8 ?reading code memory? . a procedure for reading executive memory is shown in table 6-2. note that in step 2, the tblpag register is set to 0x80, such that executive memory may be read. table 6-2: reading executive memory command (binary) data (hex) description step 1: exit the reset vector. 0000 0000 0000 0000 000000 000000 040200 000000 nop nop goto 0x200 nop step 2: initialize tblpag and the read pointer (w6) for tblrd instruction. 0000 0000 0000 200800 880190 eb0300 mov #0x80, w0 mov w0, tblpag clr w6 step 3: initialize the write pointer (w7) to point to the visi register. 0000 207847 mov #visi, w7 step 4: read and clock out the contents of the next two locations of executive memory through the visi register using the regout command. 0000 0000 0000 0000 0001 0000 0000 0000 0001 000000 ba1b96 000000 000000 ba9bb6 000000 000000 nop tblrdl [w6], [w7] nop nop clock out contents of visi register tblrdh [w6++], [w7] nop nop clock out contents of visi register step 5: reset the device internal pc. 0000 0000 040200 000000 goto 0x200 nop step 6: repeat steps 4-5 until all 2048 instruction words of executive memory are read.
DSPIC33F/pic24h programming specification ds70152d-page 72 preliminary ? 2007 microchip technology inc. 7.0 device id the device id region of memory can be used to determine mask, variant and manufacturing information about the chip. the device id region is 2 x 16-bits and it can be read using the readc command. this region of memory is read-only and can also be read when code protection is enabled. table 7-1 shows the device id for each device, table 7-2 shows the device id registers and table 7-3 describes the bit field of each register. table 7-1: device ids device devid devrev DSPIC33Fj64gp206 0xc1 0x3000 DSPIC33Fj64gp306 0xcd 0x3000 DSPIC33Fj64gp310 0xcf 0x3000 DSPIC33Fj64gp706 0xd5 0x3000 DSPIC33Fj64gp708 0xd6 0x3000 DSPIC33Fj64gp710 0xd7 0x3000 DSPIC33Fj128gp206 0xd9 0x3000 DSPIC33Fj128gp306 0xe5 0x3000 DSPIC33Fj128gp310 0xe7 0x3000 DSPIC33Fj128gp706 0xed 0x3000 DSPIC33Fj128gp708 0xee 0x3000 DSPIC33Fj128gp710 0xef 0x3000 DSPIC33Fj256gp506 0xf5 0x3000 DSPIC33Fj256gp510 0xf7 0x3000 DSPIC33Fj256gp710 0xff 0x3000 DSPIC33Fj64mc506 0x89 0x3000 DSPIC33Fj64mc508 0x8a 0x3000 DSPIC33Fj64mc510 0x8b 0x3000 DSPIC33Fj64mc706 0x91 0x3000 DSPIC33Fj64mc710 0x97 0x3000 DSPIC33Fj128mc506 0xa1 0x3000 DSPIC33Fj128mc510 0xa3 0x3000 DSPIC33Fj128mc706 0xa9 0x3000 DSPIC33Fj128mc708 0xae 0x3000 DSPIC33Fj128mc710 0xaf 0x3000 DSPIC33Fj256mc510 0xb7 0x3000 DSPIC33Fj256mc710 0xbf 0x3000 pic24hj64gp206 0x41 0x3000 pic24hj64gp210 0x47 0x3000 pic24hj64gp506 0x49 0x3000 pic24hj64gp510 0x4b 0x3000 pic24hj128gp206 0x5d 0x 3000 pic24hj128gp210 0x5f 0x 3000 pic24hj128gp306 0x65 0x 3000 pic24hj128gp310 0x67 0x 3000 pic24hj128gp506 0x61 0x 3000 pic24hj128gp510 0x63 0x 3000 pic24hj256gp206 0x71 0x 3000 pic24hj256gp210 0x73 0x 3000 pic24hj256gp610 0x7b 0x 3000 DSPIC33Fj12gp201 0x802 0x3000 DSPIC33Fj12gp202 0x803 0x3000 DSPIC33Fj12mc201 0x800 0x3000 DSPIC33Fj12mc202 0x801 0x3000 pic24hj12gp201 0x80a 0x3000 pic24hj12gp202 0x80b 0x3000
? 2007 microchip technology inc. preliminary ds70152d-page 73 DSPIC33F/pic24h prog ramming specification table 7-2: DSPIC33F/pic24h programming specification device id registers table 7-3: device id bits description address name bit 1514131211109876543210 0xff0000 devid mask<9:0> variant<5:0> 0xff0002 devrev proc<3:0> rev<5:0> dot<5:0> bit field register description mask<9:0> devid encodes the maskset id of the device. variant<5:0> devid encodes the variant derived from maskset of the device. proc<3:0> devrev encodes the process of the device. rev<5:0> devrev encodes the major revision number of the device. dot<5:0> devrev encodes the minor revision number of the device.
DSPIC33F/pic24h programming specification ds70152d-page 74 preliminary ? 2007 microchip technology inc. 8.0 ac/dc characteristics and timing requirements table 8-1 lists ac/dc characteristics and timing requirements. table 8-1: ac/dc characteristics and timing requirements standard operating conditions operating temperature: ?40 c-85 c. programming at 25 c is recommended. param no. symbol characteristic min max units conditions d111 v dd supply voltage during programming v ddcore 3.60 v normal programming (1) d112 i pp programming current on mclr ?5 a d113 i ddp supply current during programming ? 2 ma d031 v il input low voltage v ss 0.2 v dd v d041 v ih input high voltage 0.8 v dd v dd v d080 v ol output low voltage ? 0.6 v i ol = 8.5 ma @ 3.6v d090 v oh output high voltage v dd ? 0.7 ? v i oh = -3.0 ma @ 3.6v d012 c io capacitive loading on i/o pin (pgd) ? 50 pf to meet ac specifications d013 c f filter capacitor value on v cap 110 f required for controller core p1 t pgc serial clock (pgc) period 136 ? ns p1a t pgcl serial clock (pgc) low time 40 ? ns p1b t pgch serial clock (pgc) high time 40 ? ns p2 t set 1 input data setup time to serial clock 15 ? ns p3 t hld 1 input data hold time from pgc 15 ? ns p4 t dly 1 delay between 4-bit command and command operand 40 ? ns p4a t dly 1 a delay between command operand and next 4-bit command 40 ? ns p5 t dly 2 delay between last pgc of command to first pgc of read of data word 20 ? ns p6 t set 2v dd setup time to mclr 100 ? ns p7 t hld 2 input data hold time from mclr 25 ? ms p8 t dly 3 delay between last pgc of command byte to pgd by programming executive 12 ? s p9a t dly 4 programming executive command processing time 10 ? s p9b t dly 5 delay between pgd by programming executive to pgd released by programming executive 15 23 s p10 t dly 6 pgc low time after programming 400 ? ns p11 t dly 7 bulk erase time 200 ? ms p12 t dly 8 page erase time 20 ? ms p13 t dly 9 row programming time 1.5 ? ms p14 t r mclr rise time to enter icsp mode ? 1.0 s p15 t valid data out valid from pgc 10 ? ns p16 t dly 10 delay between last pgc and mclr 0?s p17 t hld 3mclr to v dd ? 100 ns note 1: v dd must also be supplied to the av dd pins during programming. av dd and av ss should always be within 0.3v of v dd and v ss , respectively.
? 2007 microchip technology inc. preliminary ds70152d-page 75 DSPIC33F/pic24h prog ramming specification p18 t key 1 delay from first mclr to first pgc for key sequence on pgd 40 ? ns p19 t key 2 delay from last pgc for key sequence on pgd to second mclr 25 ? ns p20 t dly 11 maximum wait time for configuration register programming 25 ms table 8-1: ac/dc characteristics and timing requirements (continued) standard operating conditions operating temperature: ?40 c-85 c. programming at 25 c is recommended. param no. symbol characteristic min max units conditions note 1: v dd must also be supplied to the av dd pins during programming. av dd and av ss should always be within 0.3v of v dd and v ss , respectively.
DSPIC33F/pic24h programming specification ds70152d-page 76 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds70152d-page 77 DSPIC33F/pic24h prog ramming specification appendix a: revision history revision c (june 2006) ? added code protection configuration register descriptions ? added information about unit id ? added erases , eraseg and erasec programming executive commands ? added checksum computation equation revision d (march 2007) ? added information specific to the DSPIC33Fj12gp201/202, DSPIC33Fj12mc201/ 202 and pic24hj12gp201/202 devices in sev- eral sections, including pinout diagrams, program memory sizes and device id values ? added specific checksum computations for all DSPIC33F and pic24h devices ? updated icsp bulk/page erase and row/byte pro- gram code examples to show externally timed operation (waiting for specific delay periods) ? added the p20 timing characteristic ? updated timing characteristics and references to the timing characteristics ? updated the icsp code examples
DSPIC33F/pic24h programming specification ds70152d-page 78 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds70152d-page 79 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, ps logo, seeval, smartsensor and the embedded control solutions company are registered trademarks of micr ochip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powe rtool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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